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Home > Events > Papers and Presentations

Papers & Presentations

Throughout the year, Rambus technology experts participate in speaking engagements at industry conferences and technical summits. Following are papers and presentations from these events.


	HOT CHIPS 20 HOT CHIPS is an annual symposium on high-performance chips that is sponsored by the IEEE Technical Committee on Microprocessors and Microcomputers. Rambus was proud to be a Gold sponsor and present the following: Presentations Terabyte Bandwidth Initiative: Architectural Considerations for Next-Generation Memory Systems


	MemCon 2008 MemCon is the largest worldwide conference and exhibition addressing the business, technology, and system design strategies for semiconductor memory and storage. Rambus was proud to be a Platinum sponsor of MemCon and present: Webcasts The Next Generation of Mobile Memory Memory System Challenges in the Multi-Core Era Presentations The Next Generation of Mobile Memory Memory System Challenges in the Multi-Core Era


	Agilent Digital Seminar Japan 2008 Yoshihito Koya, Rambus Marketing Manager, presented the following at Agilent Digital Seminar Japan 2008. Presentations デジタルコンシューマアプリケーション向けXDR™ DRAMの優位性


	Rambus Design Seminar Hsinchu 2008 Rambus Design Seminar Taiwan explored the future of high-performance memory designs: Types of memory systems required for next generation consumer applications and how these advanced memory systems will solve tomorrow's system challenges Innovative techniques developed by Rambus to improve memory performance and reduce overall system costs Solutions to multi-GHz memory designs Rambus' latest development initiative, the Terabyte Bandwidth Initiative, which enables 1 TB/s of memory bandwidth performance into a single SoC Presentations Rambus Memory Technologies Update Qimonda XDR™ DRAM Elpida DRAM Solutions to Advanced Digital Consumer Electronic Systems Terabyte Bandwidth Initiative XDR™ Memory Architecture for Next Generation Consumer Products XDR™ Package/PCB Design & XIO Emulation Validation of DDR and XDR™ Designs High Frequency Signal Integrity Analysis


	DVCon 2008 DVCon is the premier conference for functional design and verification of digital electronic systems. Rambus was proud to present the following papers at DVCon 2008. Papers Functional Verification in the Presence of Linear Analog Circuits CoverMore: A Methodology to deliver re-usable and verifiable design IP


	Rambus Design Seminar Bangalore 2008 Rambus Design Seminar Bangalore explored the future of high-performance memory designs: Types of memory systems required for next generation consumer applications and how these advanced memory systems will solve tomorrow's system challenges Innovative techniques developed by Rambus to improve memory performance and reduce overall system costs Rambus' latest development initiative, the Terabyte Bandwidth Initiative, which enables 1 TB/s of memory bandwidth performance into a single SoC Presentations The Evolution of Memory Architecture: The Era of Throughput Memory XDR™/XDR2 & Memory Requirements for Next Generation Consumer Products Solving System Engineering Challenges in High Speed Memory Designs Rambus DDR2/3 Memory Controller Terabyte Bandwidth Initiative: Architectural Considerations for Next-Generation Memory Systems


	DesignCon 2008 DesignCon is Silicon Valley's premier conference and technology exhibition for the semiconductor and electronic design engineering communities. Rambus was proud to be the Corporate Partner for DesignCon 2008 and present the following papers. Papers In Situ Characterization of High Speed Signaling Systems with On Chip Measurements How to find if my Checker is Complete and Exhaustive? Study of Signal and Power Integrity Challenges in High-Speed Memory I/O Designs Using Single-Ended Signaling Schemes Half-Rate Decision-Feedback Equalization – Di-Bit Response Analysis and Evaluation Analyzing the Impact of Simultaneous Switching Noise on System Margin in Gigabit Single-Ended Memory Systems Mixed-Signal Integration: Functional Verification in the Presence of Linear Analog Components


	International Conference on VLSI Design and Embedded Systems 2008 This joint-conference is a forum for researchers and designers to present and discuss various aspects of VLSI design, electronic design automation (EDA), enabling technologies, and embedded systems. It covers the entire spectrum of activities in the two vital areas of VLSI and embedded systems, which underpin the semiconductor industry. Rambus was proud to be a Gold sponsor and present the following. Presentations Memory Requirements in Next-generation Designs High-performance Memory for Next-generation Electronic Systems


	Rambus Developer Forum Japan 2007 Rambus Developer Forum (RDF) Japan is an annual Rambus-sponsored event that draws close to 1,000 visitors from the greater Tokyo region, including customers and partners from throughout Asia Pacific. Presentations Keynote: High-Bandwidth Solutions for Next-Generation Digital Electronics - Harold Hughes, Rambus Why Design Must Change: Rethinking Digital Design - Mark Horowitz, Rambus Track 1: Rambus Leadership Technology Computing Trends and Applications Driving Memory Performance - Steven Woo, Rambus Architectural Considerations for Next-Generation Memory Systems - Rich Perego, Rambus Verification Methods for High Performance Memory Systems - Arun Vaidyanath, Rambus Track 2: XDR Applications Elpida XDR™ DRAM - Toru Ishikawa, Elpida Track 3: Design Verification & Measurement 高速化するメモリの効率的測定手法とデバッグのポイント - Tatsuo Yoda, Agilent 第3世代のシリアル規格にも対応する超広帯域オシロスコープについて - Hitoshi Hatakeyama, Tektronix Ensuring Quality and Productivity Integrating Design and Verification IP - Avi Behar, Cadence Track 4: Sytem Timing Budgeting and Power Integrity for High Speed I/O Systems System Timing Budget: Past, Present, and Future - Chuck Yuan, Rambus Minimizing Timing Jitter and System Cost with Optimized Power Distribution Network Design - Ralf Schmitt, Rambus Track 5: Low Power Technology Acheiving Very Low Power in High-Performance I/O - Robert Palmer, Rambus Track 6: High Performance Sytem Enginnering: From Design to Mass Production 高速インタフェイスのシステム・エンジニアリング - Wai-Yeung Yip, Rambus Track 7: DDR2/3 Memory Controller Interfaces DDR3 Memory Controller Interface Solution for Consumer Applications - Yoshihito Koya, Rambus 高速メモリインタフェイスのシステム評価を考慮した設計 - Yoshie Nakabayashi, Rambus Track 8: Memory Controller Solutions Optimizing the Performance of DDR2/3 Memory Controller - Praveen Prakash, Rambus Transitioning to Next Generation Memory Architecture for Digital Consumer Applications - Prakash Bare, Rambus


	Rambus Developer Forum Taiwan 2007 Driving high-performance memory solutions was the focus of Rambus Developer Forum Taiwan 2007. Following are presentations from this event. Presentations XDR™ and XDR2 Overview Elpida XDR™ DRAM XDR™ System Design XDR™ System Clocking Advantages Thermal Design and Testing Considerations for Digital Home Appliances XDR™ & DDR1/2/3 Validation & Debug Solution DDR3 Memory Controller Interface Solution for Consumer Applications DDR3 Controller Characterization Elpida DRAM Solutions to Advanced Digital Consumer Electronic Systems Optimizing the Performance of DDR2/3 Memory Controller Best of Breed PCI Express® Solution Verifying DDR2 SDRAM & FB-DIMM Signal Integrity


	Rambus Design Seminar Europe 2007 The Rambus Design Seminar series in Europe explored the types of memory systems required for next-generation consumer applications and how advanced memory systems will solve today's and tomorrow's system challenges. To learn more, download presentations from this event. Presentations Addressing Memory Needs of Next Generation Digital TV’s and Set-Top Boxes Low Power Signaling Technology What is Best Suited for Your Application: DDR, GDDR or XDR Solving System Design Challenges in High Speed Memory Applications


	CDNLive! Silicon Valley 2007 CDNLive! is a global series of technical conferences where Cadence® technology users and other industry experts can network and exchange ideas. Rambus was proud to participate in CDNLive! Silicon Valley 2007 and present the following. Presentations Integrating Design IP and Verification IP to Ensure Quality and Predictability

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