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DDR3 SDRAM is being used in many computing systems today and offers data rates of up to 1600Mbps. To achieve performance levels beyond DDR3, future main memory subsystems must attain faster data rates while maintaining low power, access ...

A 5Gb/s signaling system was designed and fabricated in TSMC’s 40nm LP CMOS process. A new clock/data skew minimization technique with a source-synchronous transmit clock delay line and integrating receiver tolerates high frequency...

See slides from Rambus Fellow Craig Hampel's presentation at the 2010 Multicore Expo. In this presentation, Mr. Hampel addresses memory architecture optimizations that can support the many threads and workloads handled by multi-core...

Rambus collaborated with IBM and Xilinx to establish a high-bandwidth interface between an IBM Power Processor and the latest Xilinx FPGAs via Rambus' FlexIO™ processor bus interface. Read this application note to learn more.

There is a general consensus that 10 Gbps copper backplane serial links will be deployed in the near future. This paper takes a look at the practical and cost effective design aspects of the 10-12.5 Gbps links as well as the feasibility ...

Simultaneous switching noise is a major performance limiter for single-ended signaling systems as data rates scale higher. This paper presents a methodology to analyze the performance of single-ended interface systems like GDDR3 in the ...

In contrast to most chip-to-chip I/O interfaces that use differential signaling, the mainstream memory interface designs are based on single-ended signaling such as SSTL or PODL. Extending the data rate for single-ended signaling beyond ...

High-speed links are required to operate at BERs typically lower than 10-12. To meet such a low BER under tight power constraints, equalizers such as DFE are widely used together with half-rate/quarter-rate sampling receive architecture ...

It has been shown that there are significant variations in backplane interconnect over environmental variations. The question remains: how to best set equalization coefficients where both high performance and low cost are required? Three...

Mixed-signal architectures, in which digital control is used to adjust the electrical characteristics of analog circuits, are an important part of modern PHY designs. Verification of these types of mixed-signal systems remains difficult,...