Press Release

Rambus Introduces Memory Controller Interface Solution for Industry-standard DDR3 DRAM

Complete, drop-in DDR3 PHY architecture enables data rates of up to 1600 MHz

Rambus Developer Forum, Hsinchu, Taiwan  - 10/17/2007   Rambus Inc. (Nasdaq: RMBS), one of the world's premier technology licensing companies specializing in high-speed memory architectures, today announced the introduction of its memory controller interface solution for industry-standard DDR3 DRAM. The fully integrated hard macro cell provides the physical layer (PHY) interface between the controller logic and DDR3 or DDR2 DRAM devices for data rates of up to 1600 MHz.

Optimized for low power and reduced silicon area, the Rambus DDR3 memory controller interface cell is designed to accommodate a broad range of applications including PC main memory, consumer electronics, servers, workstations, and network communications. To serve these applications, Rambus has architected and developed a DDR3 memory controller interface macro-cell that engineers can seamlessly integrate into their customer owned tooling (COT) or application-specific integrated circuit (ASIC) chip.

"As signaling frequencies of mainstream DDR DRAMs continue to increase, the memory interfaces critical to system performance have become very challenging to design," said Martin Scott, senior vice president of engineering at Rambus Inc. "Using our extensive signal integrity experience, we have architected a low-risk, highly optimized DDR3 memory controller interface that meets the performance requirements of both main memory and consumer applications."

To ensure first-silicon success, a reliable system environment for high-volume production, and rapid in-system qualification, the Rambus DDR3 interface solution incorporates Rambus innovations such as:

  • FlexPhase™ timing adjustment circuits for precise on-chip data alignment with the clock
  • Calibrated output drivers
  • On-die termination
  • LabStation™ software environment for bring-up, characterization and validation of the DDR3 interface in the end-user application

Other key interface features include:

  • 800 to 1600 MHz data rates
  • Support for DDR3 and DDR2 signaling modes
  • On-chip phase-locked loop (PLL)
  • On-chip delay-locked loop (DLL)
  • Levelization support for fly-by command and address architecture
  • Rambus FlexPhase™ based in-PHY module that provides characterization and testing capability in the production system
  • Multi-drop bus and multi-rank module support for large capacity systems
  • Variable data bit-widths (8-, 16-, 32-, and 64-bit) with optional ECC support

Rambus DDR cells are supported by comprehensive system design and integration services that include a complete set of design models and integration tools, including GDSII database, timing models, layout verification netlists, gate-level models, place-and-route outline, and placement guidelines. Package design and system board layout services are also available. For more information about the Rambus DDR3 memory controller interface please visit www.rambus.com/ddr.

关于Rambus Inc.

Rambus 是全球首屈一指的专长于高速芯片接口发明与设计的技术授权企业。公司始建于1990 年，其专利的创新技术、突破性技术以及著名的集成专家经验帮助业内领先的芯片与系统企业向市场上推出卓越产品。Rambus 的技术与产品能够解决客户最复杂的芯片与系统级接口难题，从而帮助计算、通信与消费电子设备实现前所未有的性能。Rambus 为其世界级的专利组合以及领先的行业标准接口系列产品发放使用授权。Rambus 总部位于加利福尼亚州Los Altos，在北卡罗来纳州、印度、德国、日本和台湾等地设有地区性办事处。了解更多信息，请访问网站 www.rambus.com.cn 。



Rambus and the Rambus logo are registered trademarks of Rambus Inc. FlexPhase and LabStation are trademarks of Rambus Inc. All other trade names are the service marks, trademarks, or registered trademarks of their respective owners.

 

Contacts

Linda Ashmore
Rambus Public Relations
(650) 947-5411
lashmore@rambus.com