XIO Controller IO Cell

The XIO cell is the high-performance, low-latency controller interface to XDR™ DRAM memory devices. Using Octal Data Rate (ODR) signaling at speeds of up to 4.0 GHz, the XIO IO cell can support bandwidths of up to 8 GB/s from a single XDR DRAM device with scalability to 16 GB/s per device. The XIO can be configured to support multiple XDR devices thus providing the necessary memory bandwidth for demanding graphics, computing and consumer electronics applications. It can be used in tandem with the XMC memory controller or integrated with the customer’s logical controller design.

The XIO macro cell is composed of one or two 12-bit request bus blocks (RQ), one control block (CTL), and a variable number of 8-bit or 9-bit (for ECC support) data blocks (DQs). The RQ block provides address and control information to the memory subsystem. The CTL block performs register access, initialization, maintenance and testability functions. Each DQ block is capable of transmitting and receiving data at up to 4.0 GHz data rates. FlexPhase™ circuits allow arbitrary per-pin DQ transmit and receive data phases eliminating the need for system trace length matching. The RQ block generates single-ended signals, while the DQ blocks transmit and receive ultra low-voltage Differential Rambus Signaling Level (DRSL) signals.

For more information on the XIO controller IO cell please see the XDR™ IO Cell technical document.