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Dateiname: Modeling and Simulation of Common Clocking Topologies for Statistical Link Simulation

Statistical link analysis has gained significant importance as high-speed interconnect designs require accurate bit error rate prediction with device jitter and noise. Currently available statistical analysis techniques focus on modeling of data channels and the impact of a clock channel is often ignored or primitively approximated using a simple receiver sampling distribution. As consequence, it ignores any jitter tracking between data and clock signals. This paper presents a general formulation to model the common jitter source between data and clock signals capturing any jitter tracking between them. The formulation also predicts any jitter amplification on clock and data channels. XDR, DDR, GDDR, PCIe and CDR-based channels are considered as examples.

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