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Dateiname: Feasibility Study of a 3.2Gb/s Memory Interface in Ultra Low-Cost LQFP Packages

The feasibility of implementing a 3.2Gb/s XDR™ memory interface using an ultra low-cost LQFP package is analyzed. The target application includes multimedia electronics such as set-top boxes and HDTVs. Due to the large inductance of the LQFP package leadframes, power integrity is a major challenge for achieving high data rates. While single-ended signaling systems such as DDR and GDDR are very difficult to operate at multi-gigabit data rates using this highly inductive LQFP package, differential signaling systems such as an XDR memory interface is more immune to supply noise and it is suitable for high data rate operations. In this paper, we demonstrate that the XDR memory system with LQFP controller package can operate reliably up to 3.2Gb/s with a memory controller. The proposed design is achieved by deploying a package/chip co-design approach, and by carefully balancing the supply noise induced jitter on different supply rails of the chip.

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