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Dateiname: Power Integrity Analysis of DDR2 Memory Systems during Simultaneous Switching Events

Simultaneous switching noise (SSN) in systems using single ended drivers poses significant design challenges as data rates continue to increase. In this paper, we analyze the impact of SSN on a DDR2 memory system using a wire-bond package for the controller and operating at 667MHz. We not only focus our attention on the supply rail where the output driver is located, but also on the other supply rails where sensitive circuits are located. We demonstrate that the noise coupled into these sensitive supply rails through either other supply rails or signals can be significant. In addition, we present a methodology for finding data patterns that cause the worst case supply noise on each supply rail. Finally, the simulated supply noise is correlated with hardware measurements to validate the modeling approach.

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Jetzt herunterladen: designcon2006schmittpaper.pdf