Download File

File Name: Analyzing the Impact of Simultaneous Switching Noise on System Margin in Gigabit Single-Ended Memory Systems

Simultaneous switching noise is a major performance limiter for single-ended signaling systems as data rates scale higher. This paper presents a methodology to analyze the performance of single-ended interface systems like GDDR3 in the presence of signal and supply noise. We present a compact model for signal and supply integrity co-simulation and study the impact of supply noise and VREF noise on the system margin. A methodology to identify minimum system margin at worst-case excitation is presented and the effectiveness of DBI noise reduction coding is investigated. Finally, the system performance for different package and motherboard implementations is compared.

Read more...

This document is only available to registered users of Rambus.com.

If you're already a Rambus.com user, sign in below.

Forgot your password?

New to Rambus? Register for an account!