Rambus Contributions to the PlayStation®3

A Way to Meet Bandwidth and Capacity Needs of Next Generation Main Memory
Signal integrity issues pose a challenge to increasing the data rates of single ended systems. This paper presents techniques that help in increasing the data rates of next generation main memory systems to 1600-3200 Mbps range without ...

Understanding the Energy Consumption of Dynamic Random Access Memories
Energy consumption has become a major constraint on the capabilities of computer systems. In large systems the energy consumed by Dynamic Random Access Memories (DRAM) is a significant part of the total energy consumption. It is possible...

Understanding the Energy Consumption of Dynamic Random Access Memories
Energy consumption has become a major constraint on the capabilities of computer systems. In large systems the energy consumed by Dynamic Random Access Memories (DRAM) is a significant part of the total energy consumption. It is possible...

Challenges and Solutions for Future Main Memory
DDR3 SDRAM is being used in many computing systems today and offers data rates of up to 1600Mbps. To achieve performance levels beyond DDR3, future main memory subsystems must attain faster data rates while maintaining low power, access ...

Memory System Challenges in the Multi-Core Era
Visit Denali's website to hear Stephen Woo's MemCon 2008 presentation, Memory System Challenges in the Multi-Core Era.

Memory Architectures for Multi-Core Computing
See slides from Rambus Fellow Craig Hampel's presentation at the 2010 Multicore Expo. In this presentation, Mr. Hampel addresses memory architecture optimizations that can support the many threads and workloads handled by multi-core...

Modeling and Simulation of Common Clocking Topologies for Statistical Link
Statistical link analysis has gained significant importance as high-speed interconnect designs require accurate bit error rate prediction with device jitter and noise. Currently available statistical analysis techniques focus on modeling...

Signal and Power Integrity for a 1600 Mbps DDR3 PHY in Wirebond Package
A DDR3 interface for a data rate of 1600MHz using a wirebond package and a low-cost system environment typical for consumer electronics products was implemented. In this environment crosstalk and supply noise are serious challenges and ...

High Performance, Low Cost DDR3- 1600Mbps+ Consumer Electronics Memory ...
Paper presents a co-design approach for low cost, high performance consumer DDR3 memory interface. Design considerations are analyzed at every hierarchy (silicon/package/PCB) to meet performance and cost constraints. Strategies for cross...

Novel Test Infrastructure and Methodology Used for Accelerated Bring-up and ...
Design-for-test (DFT) techniques are continuously used in designs to help identify defects during silicon manufacturing. However, prior to production, a significant amount of time and effort is needed to bring-up and validate various ...

Power Integrity Analysis of DDR2 Memory Systems during Simultaneous ...
Simultaneous switching noise (SSN) in systems using single ended drivers poses significant design challenges as data rates continue to increase. In this paper, we analyze the impact of SSN on a DDR2 memory system using a wire-bond ...

Feasibility Study of a 3.2Gb/s Memory Interface in Ultra Low-Cost LQFP Packages
The feasibility of implementing a 3.2Gb/s XDR™ memory interface using an ultra low-cost LQFP package is analyzed. The target application includes multimedia electronics such as set-top boxes and HDTVs. Due to the large inductance of the ...

Modeling and Correlation of Supply Noise for a 3.2GHz Bidirectional ...
This paper describes the modeling of power supply noise in a high-bandwidth XDR™ DRAM memory system and the correlation with measurement results in time domain while the system is operating. A supply network model is presented that ...

DDR3 Memory Interface Solution Brief
As the performance of consumer electronics continues its rapid rise, memory interfaces are an increasingly critical part of the overall system solution. Using patented innovations and advanced circuit techniques, Rambus’ DDR3 memory ...

Creating a Generic Behavioral Model – DDR based memory system using SystemC/TLM
In a typical design cycle, the behavioral models represent an executable architecture to be used for architectual explorations and performance analysis, as well as in customer simulations. They are required to stay ahead of RTL with ...

XDR™ DRAM Product Brief
The Rambus XDR DRAM achieves an order of magnitude increase in DRAM bandwidth over todayʼs best-of-class memory systems. The XDR DRAM interface uses a small number of very high-speed signals to carry all address, data, and control ...

XDR™ Technology Summary
The Rambus XDR DRAM achieves an order of magnitude increase in DRAM bandwidth while using the fewest ICs. The XDR Interface uses a small number of very high-speed signals to carry all address, data, and control information. XDR ...

XDR™ Memory Controller Interface Brief
The Rambus XDR DRAM achieves an order of magnitude increase in DRAM bandwidth over today's best-of-class memory systems. The XDR Interface uses a small number of very high-speed signals to carry all address, data, and control ...

XDR™ DRAM 8x4Mx16/8/4/2
The Rambus XDR™ DRAM device is a general-purpose high-performance memory device suitable for use in a broad range of applications, including computer memory, graphics, video, and any other application where high bandwidth and low latency...

XDR™ DRAM 8x4Mx16
The Rambus XDR™ DRAM device is a general-purpose high-performance memory device suitable for use in a broad range of applications, including computer memory, graphics, video, and any other application where high bandwidth and low latency...

Assessing Memory Bandwidth Needs for Next-Generation Digital TVs with ...
Authored in conjunction with Philips Consumer Electronics The most common memory solutions for designing high-performance consumer DTV systems are XDR™ and DDR2. Both these consumer DRAM memories are available from top suppliers ...

XDR™ IO Cell
The Rambus XDR™ IO Cell (XIO) is a high-performance, low latency controller interface to XDR-based DRAM memory systems. The XIO is a versatile CMOS macro cell that can be seamlessly integrated into a wide variety of target processes. The...

XDR™ Architecture
Rambus XDR™ technology has been designed to support a broad range of applications and component implementations spanning multiple technology generations. The XDR architecture comprises three primary semiconductor components: XDR DRAM XDR...

XDR™ Clock Generator
The XDR™ Clock Generator provides the necessary clock signals to support XDR memory subsystem and Redwood logic interface using a reference clock input with or without spread spectrum modulation. Contained in a 28-pin TSSOP package that ...