Medienbibliothek durchsuchen
Die Medienbibliothek von Rambus ist eine Sammlung an Videos, Präsentationen und Fachbeiträgen. Geben Sie unten ein Thema ein, nach dem gesucht werden soll (z. B. „XDR2“ oder „DRAM“). Die Suche kann nach Technologie, Veranstaltung oder Jahr eingegrenzt werden. Suchen Sie beispielsweise nach einer Publikation, die auf der DesignCon 2009 herausgegeben wurde, wählen Sie „Any Technology“, „DesignCon“ und „2009“ aus.
Results 1 - 10 of 37 total results for "*"
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DDR3 SDRAM is being used in many computing systems today and offers data rates of up to 1600Mbps. To achieve performance levels beyond DDR3, future main memory subsystems must attain faster data rates while maintaining low power, access ...
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A 5Gb/s signaling system was designed and fabricated in TSMC’s 40nm LP CMOS process. A new clock/data skew minimization technique with a source-synchronous transmit clock delay line and integrating receiver tolerates high frequency...
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See slides from Rambus Fellow Craig Hampel's presentation at the 2010 Multicore Expo. In this presentation, Mr. Hampel addresses memory architecture optimizations that can support the many threads and workloads handled by multi-core...
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Rambus collaborated with IBM and Xilinx to establish a high-bandwidth interface between an IBM Power Processor and the latest Xilinx FPGAs via Rambus' FlexIO™ processor bus interface. Read this application note to learn more.
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Simultaneous switching noise is a major performance limiter for single-ended signaling systems as data rates scale higher. This paper presents a methodology to analyze the performance of single-ended interface systems like GDDR3 in the ...
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In contrast to most chip-to-chip I/O interfaces that use differential signaling, the mainstream memory interface designs are based on single-ended signaling such as SSTL or PODL. Extending the data rate for single-ended signaling beyond ...
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There is a general consensus that 10 Gbps copper backplane serial links will be deployed in the near future. This paper takes a look at the practical and cost effective design aspects of the 10-12.5 Gbps links as well as the feasibility ...
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The signal integrity effects of lowered impedance and induced crosstalk are well understood when signals traverse through the PTH vias. However, the signal integrity impact on trace impedance and crosstalk in the vertical direction ...
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The majority of today’s memory interfaces use single-ended signaling instead of differential signaling. The major drawbacks of single-ended signaling include crosstalk, power supply noise, SSO noise, and VREF noise. Although the ...
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Design-for-test (DFT) techniques are continuously used in designs to help identify defects during silicon manufacturing. However, prior to production, a significant amount of time and effort is needed to bring-up and validate various ...
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