Medienbibliothek durchsuchen
Die Medienbibliothek von Rambus ist eine Sammlung an Videos, Präsentationen und Fachbeiträgen. Geben Sie unten ein Thema ein, nach dem gesucht werden soll (z. B. „XDR 2“ oder „DRAM“). Die Suche kann nach Technologie, Veranstaltung oder Jahr eingegrenzt werden. Suchen Sie beispielsweise nach einer Publikation, die auf der DesignCon 2009 herausgegeben wurde, wählen Sie „Any Technology“, „DesignCon“ und „2009“ aus.
Results 1 - 10 of 38 total results for "*"
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Energy consumption has become a major constraint on the capabilities of computer systems. In large systems the energy consumed by Dynamic Random Access Memories (DRAM) is a significant part of the total energy consumption. It is possible...
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A 5Gb/s signaling system was designed and fabricated in TSMC’s 40nm LP CMOS process. A new clock/data skew minimization technique with a source-synchronous transmit clock delay line and integrating receiver tolerates high frequency ...
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DDR3 SDRAM is being used in many computing systems today and offers data rates of up to 1600Mbps. To achieve performance levels beyond DDR3, future main memory subsystems must attain faster data rates while maintaining low power, access ...
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See slides from Rambus Fellow Craig Hampel's presentation at the 2010 Multicore Expo. In this presentation, Mr. Hampel addresses memory architecture optimizations that can support the many threads and workloads handled by multi-core...
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Rambus collaborated with IBM and Xilinx to establish a high-bandwidth interface between an IBM Power Processor and the latest Xilinx FPGAs via Rambus' FlexIO™ processor bus interface. Read this application note to learn more.
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Simultaneous switching noise is a major performance limiter for single-ended signaling systems as data rates scale higher. This paper presents a methodology to analyze the performance of single-ended interface systems like GDDR3 in the ...
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A DDR3 interface for a data rate of 1600MHz using a wirebond package and a low-cost system environment typical for consumer electronics products was implemented. In this environment crosstalk and supply noise are serious challenges and ...
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In contrast to most chip-to-chip I/O interfaces that use differential signaling, the mainstream memory interface designs are based on single-ended signaling such as SSTL or PODL. Extending the data rate for single-ended signaling beyond ...
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Signal integrity issues pose a challenge to increasing the data rates of single ended systems. This paper presents techniques that help in increasing the data rates of next generation main memory systems to 1600-3200 Mbps range without ...
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Paper presents a co-design approach for low cost, high performance consumer DDR3 memory interface. Design considerations are analyzed at every hierarchy (silicon/package/PCB) to meet performance and cost constraints. Strategies for cross...
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