Mobile XDR™ Controller IO Cell

The Mobile XDR™ Controller IO Cell (MIO) is a high-performance, low-power, low-latency controller for Mobile XDR DRAM devices. The MIO combines Very-Low-Swing Differential (VLSD) signaling with a Fully Differential Memory Architecture (FDMA) to support data rates of 3.2 to 4.3Gbps while maintaining very low power.

The MIO cell is a versatile CMOS macro cell that can be integrated into a wide variety of processes and can be optimized for specific system requirements including bandwidth, performance and power-efficiency. This combination of flexibility, high-performance and low-power meets the demanding requirements of next-generation mobile applications.

The MIO cell can be configured for data widths of x8, x16, or x32. Each byte-wide macro of the MIO is composed of an 8-bit data block (DQ), a Command and Address block (C/A), an Advanced Power State Management Mode control block (Mode) and a Clock (CK). The DQ block consists of 8 differential links capable of signaling up to 4.3Gbps. The C/A block provides the command and address information to the DRAM using high-speed differential signaling running at full speed. As part of the Advanced Power State Management, the Mode block is responsible for initialization as well as signaling transitions in and out of power-saving modes delivering optimized power efficiency across a broad range of usage profiles. The CK signal is part of the FlexClocking™ Architecture which is a clock-forwarded and clock-distributed architecture that eliminates the need for a DLL on the DRAM. This reduces power and simplifies the DRAM interface.

The MIO has an internal interface that enables connection to a Mobile XDR Memory Controller (MMC). The MMC is a highly configurable digital memory controller designed to optimize the power and performance of the Mobile XDR memory system.