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The Rambus Media Library is a collection of videos, presentations, and technical papers. To get started, enter a topic to search on (such as "XDR2" or "mobile") below. You can also refine your search by a specific technology, event, or year. For example, if you wanted a paper that was presented at DesignCon 2009, you would select "Any Technology," "DesignCon," and "2009."
Results 1 - 10 of 31 total results for "*"
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DDR3 SDRAM is being used in many computing systems today and offers data rates of up to 1600Mbps. To achieve performance levels beyond DDR3, future main memory subsystems must attain faster data rates while maintaining low power, access ...
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A 5Gb/s signaling system was designed and fabricated in TSMC’s 40nm LP CMOS process. A new clock/data skew minimization technique with a source-synchronous transmit clock delay line and integrating receiver tolerates high frequency...
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See slides from Rambus Fellow Craig Hampel's presentation at the 2010 Multicore Expo. In this presentation, Mr. Hampel addresses memory architecture optimizations that can support the many threads and workloads handled by multi-core...
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Rambus collaborated with IBM and Xilinx to establish a high-bandwidth interface between an IBM Power Processor and the latest Xilinx FPGAs via Rambus' FlexIO™ processor bus interface. Read this application note to learn more.
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Simultaneous switching noise is a major performance limiter for single-ended signaling systems as data rates scale higher. This paper presents a methodology to analyze the performance of single-ended interface systems like GDDR3 in the ...
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In contrast to most chip-to-chip I/O interfaces that use differential signaling, the mainstream memory interface designs are based on single-ended signaling such as SSTL or PODL. Extending the data rate for single-ended signaling beyond ...
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There is a general consensus that 10 Gbps copper backplane serial links will be deployed in the near future. This paper takes a look at the practical and cost effective design aspects of the 10-12.5 Gbps links as well as the feasibility ...
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Simultaneous switching noise (SSN) in systems using single ended drivers poses significant design challenges as data rates continue to increase. In this paper, we analyze the impact of SSN on a DDR2 memory system using a wire-bond ...
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High-speed links are required to operate at BERs typically lower than 10-12. To meet such a low BER under tight power constraints, equalizers such as DFE are widely used together with half-rate/quarter-rate sampling receive architecture ...
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Third-party IP designs, such as a PCI Express IP, need to work in several different customer configurations. This presents a unique verification challenge of creating verification environments that are modular and re-usable. The reuse ...
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