Terabyte Bandwidth Initiative
The Rambus Terabyte Bandwidth Initiative reflects Rambus' ongoing commitment to innovation in cutting-edge performance memory architectures to enable tomorrow's most exciting gaming and graphics products. Targeting a terabyte per second (TB/s) of memory bandwidth (1 terabyte = 1,024 gigabytes) from a single System-on-Chip (SoC), Rambus has pioneered new memory technologies capable of signaling at 20 gigabits per second (Gbps) while maintaining best-in-class power efficiency. In order to enable the transition from current generation memory architectures, Rambus has developed innovations that support both single-ended and differential memory interfaces in a single SoC package design with no additional pins.
The patented Rambus innovations that enable this breakthrough performance, unmatched power efficiency and multi-modal functionality include:
- 32X Data Rate – Enables high data rates while maintaining a low frequency system clock.
- Fully Differential Memory Architecture (FDMA) – Improves signal integrity and reduces power consumption at high-speed operation.
- FlexLink™ Command/Address (C/A) – Reduces the number of pins required for the C/A link.
- FlexMode™ Interface – Provides multi-modal functionality, either single-ended or differential in a single SoC package design with no additional pins.
These innovations offer increased performance, higher and scalable data bandwidth, area optimization, enhanced signal integrity, and multi-modal capability for gaming, graphics and multi-core computing applications. With these innovations and others developed through the Terabyte Bandwidth Initiative, Rambus will provide the foundation for future memory architectures over the next decade.
Graphics cards and game consoles continue to be the marquee performance products for consumers. The insatiable demand for photorealistic game play, 3D images, and a richer end-user experience is constantly pushing system and memory requirements higher. Today's high-end graphics processors support as much as 128 gigabytes per second (GB/s) of memory bandwidth, and future generations will push memory bandwidth to upwards of 1 terabyte per second (TB/s).
However, increased data rates will be only one of the challenges for future graphics processors and game consoles. Historically, as performance has increased, so have power consumption and the physical size of the processor; two trends that cannot continue unchecked due to the physical limitations for both thermals and manufacturing. Future generation gaming and graphics memory systems must be able to deliver ultra-high bandwidth without significantly increasing the power consumption or pin count over current solutions.
Rambus' Terabyte Bandwidth Initiative incorporates breakthrough innovations to achieve 1TB/s of bandwidth on a single (SoC). These patented innovations include:
- 32X Data Rate transfers 32 bits of data per I/O on each clock cycle.
- Asymmetric Equalization improves overall signal integrity while minimizing the complexity and cost of the DRAM device.
- Enhanced Dynamic Point to Point (DPP) enables increased scaling of memory system capacity and access granularity.
- Enhanced FlexPhase™ Timing Adjustment enables flexible phase relationships between signals, allowing precise on-chip alignment of data with clock.
- FlexPhase circuit enhancements improve sensitivity and capability for very high performance memory systems operating at data rates of 10Gbps and higher.
- FlexLink C/A is the industry's first full-speed, scalable, point-to-point command/address implemented through a single, differential, high-speed communications channel.
- FlexMode Interface is a programmable assignment of signaling I/Os as data (DQ) or C/A, for either a single-ended or differential interface.
- FDMA is the industry's first memory architecture that incorporates differential signaling technology on all key signal connections between the memory controller and the DRAM.
- Jitter Reduction Technology improves the signal integrity of very high-speed communications links.