Terabyte Bandwidth Initiative Innovations

Rambus’ Terabyte Bandwidth Initiative incorporates breakthrough innovations to achieve a terabyte per second (TB/s) of bandwidth on a single System-on-Chip (SoC). These innovations, available for licensing, include:

• 32X Data Rate transfers 32 bits of data per I/O on each clock cycle. This is 16 times as many data bits as the double data rate (DDR) techniques common in many DRAM products today.
• Asymmetric Equalization enables very high bandwidths on next generation memory systems. Signal equalization is applied asymmetrically across the memory controller - DRAM communication link and improves overall signal integrity while minimizing the complexity and cost of the DRAM device.
• Enhanced Dynamic Point to Point (DPP) enables the performance, scalability and capacity needs of next generation memory systems. DPP now supports FlexLink™ Command/Address (C/A) allowing dynamic point-to-point capability for command/address signals. DPP enables the scaling of memory system capacity and access granularity.
• Enhanced FlexPhase™ Timing Adjustment enables flexible phase relationships between signals, allowing precise on-chip alignment of data with clock. FlexPhase enhancements improve the sensitivity and capability of FlexPhase for very high performance memory systems operating at data rates of 10 gigabits per second (Gbps) and higher.
• FlexLink C/A is the industry’s first full-speed, scalable point-to-point command/address channel. It provides the command and address information to a DRAM using a single, differential high speed communications channel.
• Fully Differential Memory Architecture (FDMA) is the industry's first memory architecture that incorporates differential signaling technology on all key signal connections between the memory controller and the DRAM. FDMA enables higher speed, lower noise and lower power in high performance memory systems.
• Jitter Reduction Technology improves the signal integrity of very high speed communications links. By reducing jitter, memory signaling performance of 16Gbps can be achieved, enabling the terabyte bandwidth performance levels of next generation memory systems.