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Results 1 - 10 of 39 total results for "*"
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Energy consumption has become a major constraint on the capabilities of computer systems. In large systems the energy consumed by Dynamic Random Access Memories (DRAM) is a significant part of the total energy consumption. It is possible...
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A 5Gb/s signaling system was designed and fabricated in TSMC’s 40nm LP CMOS process. A new clock/data skew minimization technique with a source-synchronous transmit clock delay line and integrating receiver tolerates high frequency ...
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DDR3 SDRAM is being used in many computing systems today and offers data rates of up to 1600Mbps. To achieve performance levels beyond DDR3, future main memory subsystems must attain faster data rates while maintaining low power, access ...
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"DDR3 1600Mbpsを動作ターゲットとして開発したDDR2/DDR3マルチモードPHY用テストチップの紹介をします。 低コスト化を実現するために4層ワイヤボンドパッケージ、4層PCBを用いるという制約を設けました。本講演では、制約下における設計指針に触れ、SI/PI解析のモデリングについて説明します。さらに、製品への組み込みを念頭において低ゲート数で設計した評価モジュールの機能、および、測定結果の紹介をします。"
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See slides from Rambus Fellow Craig Hampel's presentation at the 2010 Multicore Expo. In this presentation, Mr. Hampel addresses memory architecture optimizations that can support the many threads and workloads handled by multi-core...
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Rambus collaborated with IBM and Xilinx to establish a high-bandwidth interface between an IBM Power Processor and the latest Xilinx FPGAs via Rambus' FlexIO™ processor bus interface. Read this application note to learn more.
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In contrast to most chip-to-chip I/O interfaces that use differential signaling, the mainstream memory interface designs are based on single-ended signaling such as SSTL or PODL. Extending the data rate for single-ended signaling beyond ...
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Simultaneous switching noise is a major performance limiter for single-ended signaling systems as data rates scale higher. This paper presents a methodology to analyze the performance of single-ended interface systems like GDDR3 in the ...
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A DDR3 interface for a data rate of 1600MHz using a wirebond package and a low-cost system environment typical for consumer electronics products was implemented. In this environment crosstalk and supply noise are serious challenges and ...
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Statistical link analysis has gained significant importance as high-speed interconnect designs require accurate bit error rate prediction with device jitter and noise. Currently available statistical analysis techniques focus on modeling...
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