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Terabyte Bandwidth Initiative Innovations
The Terabyte Bandwidth Initiative is the latest in a long tradition of pioneering Rambus technology development programs. For more than seventeen years, Rambus engineering teams have developed the leadership innovations that enable faster signaling and advanced system designs. Committed to the advanced research and development of high-speed memory architectures, Rambus invests heavily in advanced circuit design, high-speed logic interfaces, low-power interface solutions, system engineering, signal integrity, verification, and testing. To date, Rambus engineers and scientists have developed innovations resulting in over 1000 issued and pending patents worldwide.
Terabyte Bandwidth Initiative Innovations
| 32X Data Rate |
Transfers 32 bits of data per I/O on each clock cycle - 16 times as many data bits as the DDR (double data rate) techniques common in many DRAM products today. |
| Asymmetric Equalization |
Enables very high bandwidths on next generation memory systems. Signal equalization is applied asymmetrically across the memory controller - DRAM communication link and improves overall signal integrity while minimizing the complexity and cost of the DRAM device. |
| Dynamic Point to Point (DPP) Enhanced1 |
Enables the performance, scalability and capacity needs of next generation memory systems. DPP now supports FlexLink™ C/A allowing dynamic point-to-point capability for command/address signals. DPP enables the scaling of memory system capacity and access granularity. |
| FlexLink™ C/A |
Industry’s first full-speed, scalable point-to-point command/address channel. FlexLink C/A provides the command and address information to a DRAM using a single, differential high speed communications channel. |
| FlexPhase™ Timing Adjustments Enhanced1 |
Enables flexible phase relationships between signals, allowing precise on-chip alignment of data with clock. FlexPhase enhancements improve the sensitivity and capability of FlexPhase for very high performance memory systems operating at data rates of 10 Gbits and higher. |
| Fully Differential Memory Architecture (FDMA) |
Industry's first memory architecture that incorporates differential signaling technology on all key signal connections between the memory controller and the DRAM. FDMA enables higher speed, lower noise and lower power in high performance memory systems. |
| Jitter Reduction Technology |
Improves the signal integrity of very high speed communications links. By reducing jitter, memory signaling performance of 16Gbps can be achieved, enabling the terabyte bandwidth performance levels of next generation memory systems. |
1 Enhanced technology capability used for the Terabyte Bandwidth Initiative
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