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파일명: Prediction and Measurement of Supply Noise Induced Jitter in High-Speed I/O Interfaces

This paper presents a systematic approach for analyzing supply noise induced timing jitter in high-speed I/O interfaces. The proposed method combines frequency-dependent supply noise jitter sensitivity profile with supply noise spectral content to predict the jitter generated by the supply noise. Distributed power grid model and device-level current profiles are used to obtain time- and frequency-domain supply noise. Jitter sensitivity is extracted by sweeping the frequency of single tone disturbance added to ideal supply. Supply noise and jitter sensitivity are also measured by auto-correlation-based on-chip noise monitor circuit. The predicted supply noise induced jitter is shown to correlate well with the measurement data for a high speed I/O interface operating at 6.4Gbps.

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지금 다운로드: 090202_designcon_paper_lan.pdf