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파일명: Half-Rate Decision-Feedback Equalization – Di-Bit Response Analysis and Evaluation

High-speed links are required to operate at BERs typically lower than 10^-12. To meet such a low BER under tight power constraints, equalizers such as DFE are widely used together with half-rate/quarter-rate sampling receive architecture [1,2,3]. In this paper, we present a statistical performance analysis method based on di-bit (two-bit) response analysis to accurately analyze the performance of links with half-rate receive architectures. Compared with single-bit response analysis, di-bit response analysis can naturally model link non-idealities such as DCD and odd/even path mismatch, as well as half-rate DFE.

We use this method to compare the performance of full-rate DFE [1] and half-rate DFE [2,3] receive architectures. Our simulation results show that compared with half-rate DFE, full-rate DFE provides better ISI cancellation at edge sample time, improving timing margin and clock recovery. Our analysis also shows that, by using PrDFE [1,4] to handle the first post-cursor at both data and edge time, in addition to the ability to handle DCD and odd/even path mismatches, half-rate DFE could provide an overall better performance with modest hardware cost.

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지금 다운로드: designcon2008renpaper.pdf