XDR and XDR™2 Memory Architecture: Performance and Power-Efficiency Demonstration

Kendra DeBerti runs through a demo of the XDR-XDR 2 Memory Architecture, highlighting a bimodal XIO memory controller and speeds up to 7.2Gbps.

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Micro-threaded Row and Column Operations in a DRAM Core The technique of micro-threading may be applied to the core of a DRAM to reduce the row and column access granularity. This results in a significant performance benefit for those applications that deal with small data objects. Read more...
XDR™2 Memory Architecture Today's powerful graphics and multi-core processors require significantly higher memory performance when compared to traditional single-core processors. Without adequate data bandwidth, memory becomes the limiting factor in delivering ...