Join Cadence and Rambus for a webinar on system-level verification of high-speed XDR™ memory
Easing the integration of IP into System-Level designs through the use of verification platforms has become a powerful methodology for improving product quality and accelerating time to market. Recently the Open Verilog Methodology (OVM) was announced along with new verification product offerings from Cadence and others to provide a SystemVerilog-based interoperable means of developing a reusable and interoperable verification suite.
This presentation will provide an overview of the methodologies used to verify the integration on high bandwidth XDR™ memory by using leveraging the Open Verilog Methodology, the development of OVM-based verification IP to complement Rambus XDR and running under the Cadence® Incisive® Enterprise Simulator environment.
Estimated Length: 35 minute presentation, 15 min Q&A
Who Should Attend?
- Systems Engineers & Architects
- Design & Verification Engineers & Managers
Prerequisites for Attendees:
- Familiarity with Verilog, preferably System Verilog
- Understanding of high speed memory architectures and requirements
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register to attend.
