FlexMode™ Interface

Rambus' FlexMode™ interface technology uses a programmable assignment of signaling pins as either data (DQ), or command/address (C/A), to enable multi-modal functionality while minimizing signal pin count across single-ended and differential signaling modes. FlexMode interface technology allows for a seamless transition to next-generation high-performance, low-power, differential memory through backward compatibility to single-ended memories such as GDDR5 and DDR3. This enables an SoC memory controller to be implemented in a single package design with no additional signal pin overhead. An SoC using FlexMode interface technology can address a broad range of system requirements, from entry-level to high-end, without additional cost.

Traditional multi-modal implementations combine the worst-case signal pin count for the functional blocks of the interface for each memory type. When combining functionality of multiple memory types with differing signaling architectures, such as single-ended and differential, this implementation technique can lead to costly design inefficiencies including increased pin count and costs.

As an example, conventional signal mapping for a 32-bit wide single-ended DDR3 and GDDR5 memory interface combined with a differential XDR™2 memory interface would combine the 64 DQ pins from the XDR 2 memory (worst case DQ) and the 31 C/A pins from the DDR3 interface (worst case C/A) for a total of 95 signal pins (see "Conventional Multi-Modal Interface" diagram). This translates to a 16 signal pin overhead versus the single-ended GDDR5/DDR3 interface.

FlexMode interface technology assigns individual pins to operate in either single-ended or differential mode, as DQ or C/A signals, to optimize total pin count in all signaling modes. Through programmable signal pin assignment, multi-modal functionality can be implemented in a single SoC package design. When operating in the single-ended GDDR5/DDR3 mode described above, the FlexMode interface pins are allocated to the wider C/A block. Conversely, when operating in XDR 2 memory mode, the FlexMode interface pins are allocated to the DQ blocks (see "FlexMode Interface Technology" diagram). This dynamic allocation minimizes the interface footprint, while enabling seamless scalability across a range of performance level.

Commercial and Performance Benefits

Rambus' FlexMode interface technology enables multi-modal functionality across differential and single-ended signaling memory types with no additional pin overhead and in a single SoC package design. By advancing data rates to up to 20 gigabits per second in an extremely power-efficient way with XDR 2 memory, and enabling compatibility to current industry-standard memories including GDDR5 and DDR3, FlexMode interface technology removes the technical and business barriers for customers to achieve unprecedented capabilities in their products.