Rambus
type: channel
description: At Rambus, we create cutting-edge semiconductor and IP products, providing industry-leading chips and silicon IP to make data faster and safer.
date: 2026-03-20T22:02:01Z
update period: hourly
update frequency: 1
update base: 2000-01-01T12:00+00:00
generator agent: https://wordpress.org/
items: COMPUTEX
items: Live Webinar: HBM4E Advances ​Bandwidth Performance for AI Training
items: D&R IP SoC Silicon Valley
items: TSMC North America Technology Symposium
items: Hardware Deployment for Secure AI Using Confidential Computing
items: Rambus DRAM Tutorial
items: HBM4E Controller Product Brief
items: HBM4E Controller

https://www.rambus.com/3e92c5df693628b809a8cef35c5b3e67/
type: item
date: 2026-03-20T22:02:01Z

COMPUTEX
type: item
date: 2026-03-18T22:25:57Z
description: We are excited to be attending COMPUTEX in Taipei, Taiwan! If you would like to schedule some time to meet with us at the show, please send us an email here or fill out our contact form here. To register and learn more about COMPUTEX, visit the page here: https://www.computextaipei.com.tw/en/index.html About COMPUTEX Established in […]
encoded: We are excited to be attending COMPUTEX in Taipei, Taiwan! If you would like to schedule some time to meet with us at the show, please send us an email here or fill out our contact form here. To register and learn more about COMPUTEX, visit the page here: https://www.computextaipei.com.tw/en/index.html About COMPUTEX Established in 1981, COMPUTEX TAIPEI (also called COMPUTEX) is the leading global ICT and IoT show with a complete supply chain and ecosystems. Co-organized by the Taiwan External Trade Development Council (TAITRA) and Taipei Computer Association (TCA), COMPUTEX, based upon Taiwan’s complete ICT clusters, covers the whole spectrum of ICT industry, from established brands to startups and from ICT supply chain to IoT ecosystems. With strong R&D and manufacturing capabilities and IPR protection, Taiwan is a strategic destination for foreign companies and investors looking for partners in global technology ecosystems.

Live Webinar: HBM4E Advances ​Bandwidth Performance for AI Training
type: item
date: 2026-03-17T23:55:04Z
description: AI training continues to push the limits of memory bandwidth, latency, and system scalability. As model sizes grow and compute density increases, memory architecture has become a defining factor in overall system performance. HBM has emerged as the memory of choice for these workloads, and HBM4E represents the next major step forward. HBM4E extends the […]
encoded: AI training continues to push the limits of memory bandwidth, latency, and system scalability. As model sizes grow and compute density increases, memory architecture has become a defining factor in overall system performance. HBM has emerged as the memory of choice for these workloads, and HBM4E represents the next major step forward. HBM4E extends the HBM roadmap to address these challenges, delivering the performance headroom required for next-generation AI and HPC platforms. Join Rambus for a technical deep dive into HBM4E and the industry-leading HBM4E Memory Controller IP. In this webinar, Nidish Kamath from Rambus will walk through the key requirements driving HBM4E adoption and introduce Rambus’ newly announced HBM4E Memory Controller IP. The session will cover how HBM4E enables higher bandwidth, improved efficiency, and scalable integration for next-generation AI accelerators, along with practical considerations for building high-performance memory subsystems. We will explore why HBM4E is ideally suited for AI training, and what system architects should consider when deploying HBM4E in advanced AI designs.
title: HBM4E Advances ​Bandwidth Performance for AI Training
date: 2026-03-12T22:57:02Z
subject: Interface IP
subject: Webinars
description: [Live on April 8 at 11am PT] Join Rambus for a technical deep dive into HBM4E and the industry-leading HBM4E Memory Controller IP. In this webinar, Nidish Kamath from Rambus will walk through the key requirements driving HBM4E adoption and introduce Rambus’ newly announced HBM4E Memory Controller IP.
encoded: [Live on April 8 at 11am PT] Join Rambus for a technical deep dive into HBM4E and the industry-leading HBM4E Memory Controller IP. In this webinar, Nidish Kamath from Rambus will walk through the key requirements driving HBM4E adoption and introduce Rambus’ newly announced HBM4E Memory Controller IP.

D&R IP SoC Silicon Valley
type: item
date: 2026-03-17T23:09:11Z
description: Join us at D&R IP SoC Silicon Valley! Stop by Table 1 and chat with our experts about our Silicon IP offerings. We will also be presenting on three topics. Session information below. From Monolithic SoCs to Chiplets: A new Hardware Security Paradigm Speaker: Berardino Carnevale, Senior Technical Marketing and Product Manager at Rambus Abstract: […]
encoded: Join us at D&R IP SoC Silicon Valley! Stop by Table 1 and chat with our experts about our Silicon IP offerings. We will also be presenting on three topics. Session information below. From Monolithic SoCs to Chiplets: A new Hardware Security Paradigm Speaker: Berardino Carnevale, Senior Technical Marketing and Product Manager at Rambus Abstract: Chiplet‑based architectures are transforming SoC design, but they also upend long‑standing security assumptions. By disaggregating a monolithic die into multiple, often multi‑vendor chiplets, the implicit silicon trust boundary disappears, expanding the attack surface to include chiplet substitution, weak‑chiplet compromise, and exposed die‑to‑die interconnects. This presentation explores why traditional SoC security models fail in chiplet systems and introduces a system‑level security paradigm based on distributed trust with centralized authority. AI Inference needs a mix-and-match memory strategy Speaker: Nidish Kamath, Director of Product Management, Silicon IP at Rambus Abstract: AI inference spans diverse workloads, from low‑latency chat to long‑context reasoning and large‑scale recommendations—making single, monolithic accelerator and memory designs increasingly inefficient. This talk explains how inference naturally splits into prefill and decode stages with fundamentally different bottlenecks: prefill is compute‑bound, while decode is dominated by memory bandwidth and latency. By matching memory technologies to each stage, using cost‑efficient GDDR or LPDDR for prefill and reserving premium HBM for decode, with pooled memory for KV offload, operators can significantly reduce cost per token without sacrificing latency. The session outlines emerging disaggregated architectures for AI inference workloads. Enabling Efficient Edge AI Inferencing Through Ecosystem Collaboration Speakers: Nidish Kamath, Director of Product Management, Silicon IP at Rambus & Kevin Yee, Sr. Director of IP and Ecosystem Marketing, Samsung Found…

TSMC North America Technology Symposium
type: item
date: 2026-03-17T23:02:35Z
description: We’re excited to be participating at TSMC North America Technology Symposium! Stop by booth #400 and learn about our solutions. To learn more and register, click the link here: https://www.tsmc.com/static/english/campaign/Symposium2026/index.htm
encoded: We’re excited to be participating at TSMC North America Technology Symposium! Stop by booth #400 and learn about our solutions. To learn more and register, click the link here: https://www.tsmc.com/static/english/campaign/Symposium2026/index.htm

Hardware Deployment for Secure AI Using Confidential Computing
type: item
date: 2026-03-17T22:57:56Z
subject: Papers
subject: Security IP
description: AI’s fast evolution is producing autonomous systems that can operate with minimal human oversight, improve themselves and become effective at decision-making in complex environments. These developments require careful consideration of security and privacy. To limit the overhead performance impact (area, throughput, latency and power), hardware-based security solutions can be deployed using state-of-the-art silicon IP.
encoded: AI’s fast evolution is producing autonomous systems that can operate with minimal human oversight, improve themselves and become effective at decision-making in complex environments. These developments require careful consideration of security and privacy. To limit the overhead performance impact (area, throughput, latency and power), hardware-based security solutions can be deployed using state-of-the-art silicon IP.

Rambus DRAM Tutorial
type: item
date: 2026-03-12T21:12:31Z
description: This tutorial will describe DRAM architecture in detail, highlighting the similarities and differences between different DRAM technologies and the unique tradeoffs and design choices made to meet system needs. We will also cover the key components that memory transactions travel thorough to get to DRAMs and back, including memory controllers, PHYs, and where applicable, modules and buffer chips. We will describe the architecture of these critical components and discuss how DRAM architecture choices impact their performance and power efficiency. Standard scaling techniques for DRAMs will be highlighted along with challenges that the industry is currently facing. Input from industry experts will show the pros and cons of DRAM architecture choices, demonstrating the system impact and requirements for mainstream adoption. Future DRAM architectures will also be discussed.
encoded: Scaling DRAM Technology to Meet Future Demands: System Challenges and Opportunities Saturday, June 27, 2026, Raleigh, North Carolina Full-Day tutorial held in conjunction with ISCA 2026 Home Tutorial Abstract Since the invention of the 1T1C bit cell more than 50 years ago, DRAMs have become the main memory of choice for processors in computing systems and consumer electronics devices. As new computing paradigms have been created, including AI, 3D graphics, HPC, cloud computing, and smart phones, specialized processors and DRAM memories have been developed that are optimized for these use cases. The same 1T1C DRAM bit cell is used in each of these applications, but the internal architecture and interfaces of the DRAMs supporting these markets are optimized in different ways, and the DRAMs are packaged differently (sometimes with additional buffer chips) to meet the needs of the system. Across all markets, there is a relentless demand for higher performance and better power efficiency, as insufficient DRAM bandwidth can bottleneck application performance and interfaces to DRAMs can consume half of the SOC power. DRAMs are also being stressed by growing reliability concerns as they incorporate on-die ECC and mitigation for disturbance effects such as RowHammer and RowPress. As AI continues to grow across markets (HPC, server, client, mobile, etc.), the design of efficient, performant and reliable memory systems is becoming increasingly critical. AI models are continuing to grow, pushing the capacity and bandwidth requirements of DRAMs. Simply scaling with historical techniques will no longer achieve the required characteristics due to physical challenges, limits of process scaling, and system architecture constraints including thermals and power delivery. This tutorial will describe DRAM architecture in detail, highlighting the similarities and differences between different DRAM technologies and the unique tradeoffs and design choices made to meet system needs. We will…

HBM4E Controller Product Brief
type: item
date: 2026-03-04T22:37:44Z
subject: Briefs
subject: Controllers
subject: Interface IP
description: Download the product to learn about the Rambus HBM4E Controller. Our HBM4E Controller is designed to support customers with deploying a new generation of HBM memory for cutting-edge AI accelerators, graphics and high-performance computing (HPC) applications.
encoded: Download the product to learn about the Rambus HBM4E Controller. Our HBM4E Controller is designed to support customers with deploying a new generation of HBM memory for cutting-edge AI accelerators, graphics and high-performance computing (HPC) applications.

HBM4E Controller
type: item
date: 2026-03-04T22:01:21Z
description: Rambus offers the industry’s fastest HBM4E Controller IP core designed to support customers with deploying a new generation of HBM memory for cutting-edge AI accelerators, graphics and high-performance computing (HPC) applications.
encoded: HBM4E Controller IP Contact Us Home Rambus offers the industry’s fastest HBM4E Controller IP core designed to support customers with deploying a new generation of HBM memory for cutting-edge AI accelerators, graphics and high-performance computing (HPC) applications. Secure Site Login Contact Product Brief How the Rambus HBM4E Controller Works The core accepts commands using a simple local interface and translates them to the command sequences required by HBM4/4E devices. The core also performs all initialization, refresh and power-down functions. The core queues up multiple commands in the command queue. This enables optimal bandwidth utilization for both short transfers to highly random address locations as well as longer transfers to contiguous address space. The command queue is also used to opportunistically perform look-ahead activates, precharges and auto-precharges, further improving overall throughput. The Reorder functionality is fully integrated into the controller command queue increasing throughput and minimizing gate count. <img fetchpriority="high" decoding="async" width="972" height="574" src="https://www.rambus.com/wp-content/uploads/2026/03/HBM4E_Controller_IP_Block_Diagram.png" class="attachment-full size-full wp-image-66087" alt="HBM4E Memory Subsystem" srcset="https://www.rambus.com/wp-content/uploads/2026/03/HBM4E_Controller_IP_Block_Diagram.png 972w, https://www.rambus.com/wp-content/uploads/2026/03/HBM4E_Controller_IP_Block_Diagram-300x177.png 300w, https://www.rambus.com/wp-content/uploads/2026/03/HBM4E_Controller_IP_Block_Diagram-150x89.png 150w, https://www.rambus.com/wp-content/uploads/2026/03/HBM4E_Controller_IP_Block_Diagram-768x454.png 768w" sizes="(max-width: 972px) 100vw, 972px" /> HBM4E Memory Subsystem The controller can be delivered standalone or integrated with the customer’s choice of HBM4E PHY to instantiate a complete HBM4E memory subsystem. Ask the Experts: HBM4 Controller IP In this episode of Ask the Experts, we discuss HBM…