Rambus
type: channel
description: At Rambus, we create cutting-edge semiconductor and IP products, providing industry-leading chips and silicon IP to make data faster and safer.
date: 2026-04-10T21:32:49Z
update period: hourly
update frequency: 1
update base: 2000-01-01T12:00+00:00
generator agent: https://wordpress.org/
items: [Live Webinar] Enabling Next‑Generation Client Memory with Rambus DDR5 CUDIMM/CSODIMM and LPCAMM2 Chipsets
items: [Live Webinar] Reliability and Supply Chain Security for the Automotive Semiconductor Industry
items: Reliability and Supply Chain Security for the Automotive Semiconductor Industry
items: MACsec Explained: Everything You Need to Know
items: Google, Quantum Attacks, and ECDSA: Why There’s No Need to Panic and Why Preparation Matters Now
items: Author Archive – Lou Ternullo
items: Rambus Recognized by Forbes as One of America’s Most Successful Mid‑Cap Companies for 2026​
items: RISC-V Now! by Andes | Shanghai
items: RISC-V Now! by Andes | Taiwan

[Live Webinar] Enabling Next‑Generation Client Memory with Rambus DDR5 CUDIMM/CSODIMM and LPCAMM2 Chipsets
type: item
date: 2026-04-10T21:32:11Z
description: As client platforms push toward higher performance, greater efficiency, and AI‑ready computing to address the latest developments in gaming, content creation and other advanced applications, memory subsystem design has become a critical differentiator. Next-generation DDR5 and LPDDR‑based memory modules demand state-of-the-art approaches to power management, clocking, and system reliability, especially as data rates scale to […]
encoded: As client platforms push toward higher performance, greater efficiency, and AI‑ready computing to address the latest developments in gaming, content creation and other advanced applications, memory subsystem design has become a critical differentiator. Next-generation DDR5 and LPDDR‑based memory modules demand state-of-the-art approaches to power management, clocking, and system reliability, especially as data rates scale to 7200 MT/s and beyond. In this webinar, Rambus experts will explore how complete client memory interface chipsets enable high‑performance DDR5 CUDIMM and CSODIMM modules operating up to 7200 MT/s, with capabilities for overclocking. Also covered will be chipsets for the latest LPCAMM2 modules designed for thin, power‑efficient client systems. Attendees will gain insight into the architectural challenges of high‑speed client memory, including signal integrity, power delivery, sideband management, and thermal considerations, and how Rambus chipset solutions address these challenges at the module level.
title: Enabling Next‑Generation Client Memory with Rambus DDR5 CUDIMM/CSODIMM and LPCAMM2 Chipsets
date: 2026-04-10T17:58:51Z
subject: Memory Interface Chips
subject: Webinars
description: n this webinar, Rambus experts will explore how complete client memory interface chipsets enable high‑performance DDR5 CUDIMM and CSODIMM modules operating up to 7200 MT/s, with capabilities for overclocking. Also covered will be chipsets for the latest LPCAMM2 modules designed for thin, power‑efficient client systems. Attendees will gain insight into the architectural challenges of high‑speed client memory, including signal integrity, power delivery, sideband management, and thermal considerations, and how Rambus chipset solutions address these challenges at the module level.
encoded: [Live on Apr 29 at 9am UTC +8) In this webinar, Rambus experts will explore how complete client memory interface chipsets enable high‑performance DDR5 CUDIMM and CSODIMM modules operating up to 7200 MT/s, with capabilities for overclocking.

[Live Webinar] Reliability and Supply Chain Security for the Automotive Semiconductor Industry
type: item
date: 2026-04-10T21:30:37Z
description: As vehicles become increasingly software‑defined and electronics‑driven, the cost of semiconductor failure, whether due to reliability issues or security breaches, has never been higher. Automotive recalls tied to electronic failures continue to rise, exposing a critical gap between existing standards compliance and real‑world field performance. While ISO 26262 and AEC‑Q100 provide an essential foundation for […]
encoded: As vehicles become increasingly software‑defined and electronics‑driven, the cost of semiconductor failure, whether due to reliability issues or security breaches, has never been higher. Automotive recalls tied to electronic failures continue to rise, exposing a critical gap between existing standards compliance and real‑world field performance. While ISO 26262 and AEC‑Q100 provide an essential foundation for functional safety and reliability, they are no longer sufficient on their own to eliminate failures across the full chip lifecycle. At the same time, semiconductor security must extend beyond protecting devices from hackers to securing the entire supply chain, from fabrication to deployment in the field. This webinar examines why reliability and security have become inseparable drivers for next‑generation automotive chips, and how a lifecycle‑based approach is required to meaningfully reduce recall risk. We will review real‑world examples of recalls caused by electronic failures, explore the evolving standards landscape driving higher expectations for reliability and traceability, and walk through the end‑to‑end chip lifecycle from wafer fabrication to in‑vehicle operation.

Reliability and Supply Chain Security for the Automotive Semiconductor Industry
type: item
date: 2026-04-10T18:00:21Z
subject: Memory Interface Chips
subject: Webinars
description: This webinar examines why reliability and security have become inseparable drivers for next‑generation automotive chips, and how a lifecycle‑based approach is required to meaningfully reduce recall risk. We will review real‑world examples of recalls caused by electronic failures, explore the evolving standards landscape driving higher expectations for reliability and traceability, and walk through the end‑to‑end chip lifecycle from wafer fabrication to in‑vehicle operation.
encoded: [Live on May 21 at 11am PT] This webinar examines why reliability and security have become inseparable drivers for next‑generation automotive chips, and how a lifecycle‑based approach is required to meaningfully reduce recall risk. We will review real‑world examples of recalls caused by electronic failures, explore the evolving standards landscape driving higher expectations for reliability and traceability, and walk through the end‑to‑end chip lifecycle from wafer fabrication to in‑vehicle operation.

MACsec Explained: Everything You Need to Know
type: item
creator: Rambus Press
date: 2026-04-08T08:00:21Z
subject: macsec
subject: protocol engines
description: [Last updated on April 8, 2026] MACsec (Media Access Control Security) is an Ethernet security standard that encrypts and authenticates data in motion at Layer 2 of the OSI model, protecting traffic as it moves between directly connected devices. To achieve end‑to‑end security, data must be secured throughout its entire lifecycle: when it is stored, […]
encoded: [Last updated on April 8, 2026] MACsec (Media Access Control Security) is an Ethernet security standard that encrypts and authenticates data in motion at Layer 2 of the OSI model, protecting traffic as it moves between directly connected devices. To achieve end‑to‑end security, data must be secured throughout its entire lifecycle: when it is stored, when it is actively processed, and when it is transmitted between devices. Hardware root of trust anchored in silicon provides foundation for securing data at rest, while inline memory encryption protects data in use. For data in motion, however, security must be enforced at the point where information first leaves the device, before it traverses a network that may not be fully trusted. This is where MACsec plays a critical role. By anchoring security in hardware at the Ethernet layer, MACsec ensures that all network traffic is encrypted and authenticated the moment it goes on the wire. This approach protects against eavesdropping, tampering, and impersonation without relying on higher‑layer software or application changes. In this blog, we’ll explore what MACsec is, how it works, how it compares to higher-layer security approaches, and why it is essential for modern Ethernet-based systems. Table of Contents: What is the OSI Model and How Does it Relate to Network Security? What Is MACsec and Why Does It Matter? How Does MACsec Work at the Ethernet Layer? How Does MACsec Authentication and Key Management Work? MACsec vs. IPsec and TLS: What’s the Difference? What Are the Performance, Latency, and Power Considerations for MACsec? Where is MACsec Used Today? Rambus MACsec IP Solutions Summary: Why MACsec Matters for Modern Ethernet Security Frequently Asked Questions about MACsec What is the OSI Model and How Does it Relate to Network Security? The OSI model explains how MACsec, IPsec, and TLS secure data at different layers of the network communication. <img fetchpriority="high" decoding="async" class="size-full wp-image-…

Google, Quantum Attacks, and ECDSA: Why There’s No Need to Panic and Why Preparation Matters Now
type: item
creator: Scott Best
date: 2026-04-06T16:24:23Z
description: Over the past several weeks, we’ve seen growing discussion across the industry about Google’s latest publications on quantum computing and cryptography. In some corners, those discussions have quickly escalated into claims that widely deployed elliptic curve cryptography (ECC), including ECDSA, is on the verge of collapse.
encoded: Over the past several weeks, we’ve seen growing discussion across the industry about Google’s latest publications on quantum computing and cryptography. In some corners, those discussions have quickly escalated into claims that widely deployed elliptic curve cryptography (ECC), including ECDSA, is on the verge of collapse. Customers are understandably asking questions: Has ECDSA been broken? Are today’s systems suddenly at risk? Do migration timelines need to change? At Rambus, our view is clear and measured: there is no need to panic, but there is every reason to prepare thoughtfully and deliberately for the post‑quantum transition already underway. What Google Has Actually Published To put recent claims into context, it’s important to separate what has been said from what has been inferred. In November 2025, Google published an academic paper outlining its perspective on the state and trajectory of quantum computing. This work reinforced a view shared by many in the research community: progress is steady and meaningful, but not sudden or magical. More recently, in March 2026, Google made two notable public moves. First, it announced plans to migrate its cryptographic infrastructure to post‑quantum cryptography (PQC) by 2029, one of the most aggressive migration timelines publicly stated by a major technology provider. Shortly thereafter, Google and academic collaborators published a white paper analyzing the impact of quantum attacks on cryptocurrencies, including an improved theoretical attack against ECDSA. That white paper, in particular, has drawn significant attention well beyond the cryptocurrency ecosystem. Has ECDSA Been “Broken”? No. Despite some dramatic headlines, ECDSA has not been broken. The improved attack described in the paper is still estimated to require hundreds of thousands of physical qubits. Today’s quantum systems are typically well below 10,000 physical qubits, and scaling reliably to that level remains a substantial technical challenge. I…

Author Archive – Lou Ternullo
type: item
date: 2026-04-02T23:04:28Z
description: About Lou Ternullo
encoded: <img decoding="async" width="400" height="400" src="https://www.rambus.com/wp-content/uploads/2023/06/Lou_Ternullo.jpg" class="attachment-full size-full wp-image-63035" alt="Lou Ternullo" srcset="https://www.rambus.com/wp-content/uploads/2023/06/Lou_Ternullo.jpg 400w, https://www.rambus.com/wp-content/uploads/2023/06/Lou_Ternullo-300x300.jpg 300w, https://www.rambus.com/wp-content/uploads/2023/06/Lou_Ternullo-150x150.jpg 150w, https://www.rambus.com/wp-content/uploads/2023/06/Lou_Ternullo-75x75.jpg 75w" sizes="(max-width: 400px) 100vw, 400px" /> About Lou Ternullo <div class="elementor-element elementor-element-8682cda elementor-grid-3 elementor-grid-tablet-2 elementor-grid-mobile-1 elementor-posts--thumbnail-top elementor-posts--show-avatar elementor-card-shadow-yes elementor-posts__hover-gradient elementor-widget elementor-widget-posts" data-id="8682cda" data-element_type="widget" data-e-type="widget" data-settings="{"pagination_type":"prev_next","cards_columns":"3","cards_columns_tablet":"2","cards_columns_mobile":"1","cards_row_gap":{"unit":"px","size":35,"sizes":[]},"cards_row_gap_tablet":{"unit":"px","size":"","sizes":[]},"cards_row_gap_mobile":{"unit":"px","size":"","sizes":[]}}" data-widget_type="posts.cards"> <img loading="lazy" decoding="async" width="500" height="286" src="https://www.rambus.com/wp-content/uploads/2025/04/abstract-tech-still.jpg" class="attachment-full size-full wp-image-65455" alt="Join us for a webinar: Unleashing the Performance of AI Training with HBM4" srcset="https://www.rambus.com/wp-content/uploads/2025/04/abstract-tech-still.jpg 500w, https://www.rambus.com/wp-content/uploads/2025/04/abstract-tech-still-300x172.jpg 300w, https://www.rambus.com/wp-content/uploads/2025/04/abstract-tech-still-150x86.jpg 150w" sizes="(max-width: 500px) 100vw, 500px" /> Accelerating AI Workloads with Composable Memory & Hardware Acceleration Join Lou Ternullo from Rambus along with Yiannis Nikolakopoulos from ZeroPoint as they discuss a solution that …

Rambus Recognized by Forbes as One of America’s Most Successful Mid‑Cap Companies for 2026​
type: item
creator: Rambus Press
date: 2026-04-02T16:41:41Z
description: Rambus is proud to announce that we have been named one of Forbes’ Most Successful Mid‑Cap Companies for 2026, ranking #21 out of 100 companies nationwide. This recognition highlights Rambus’ sustained financial performance, disciplined execution, and continued focus on delivering differentiated semiconductor technologies that address the world’s most demanding compute challenges. ©2026 Forbes Media LLC. […]
encoded: Rambus is proud to announce that we have been named one of Forbes’ Most Successful Mid‑Cap Companies for 2026, ranking #21 out of 100 companies nationwide. This recognition highlights Rambus’ sustained financial performance, disciplined execution, and continued focus on delivering differentiated semiconductor technologies that address the world’s most demanding compute challenges. <img loading="lazy" decoding="async" class="alignnone size-full wp-image-66275" src="https://www.rambus.com/wp-content/uploads/2026/04/Forbes-Blog.png" alt="Rambus is named one of Forbes' Most Successful Midsize Companies!" width="600" height="230" srcset="https://www.rambus.com/wp-content/uploads/2026/04/Forbes-Blog.png 600w, https://www.rambus.com/wp-content/uploads/2026/04/Forbes-Blog-300x115.png 300w, https://www.rambus.com/wp-content/uploads/2026/04/Forbes-Blog-150x58.png 150w" sizes="(max-width: 600px) 100vw, 600px" /> ©2026 Forbes Media LLC. All rights reserved. Used under license. ​​ Each year, Forbes evaluates publicly traded mid‑cap companies with market capitalizations between $5 billion and $20 billion, using data from FactSet. To qualify, companies must demonstrate positive sales growth over the past year and meet additional financial criteria. The final rankings are based on earnings growth, sales growth, return on equity, and total stock return over the past five years, with greater emphasis placed on the most recent year’s performance. All data for the 2026 ranking reflects results as of December 5, 2025.​ Rambus’ placement on this list reflects the strength of our long‑term strategy and the impact of our product portfolio across memory interface chips, interface IP, and security IP solutions. As data volumes continue to grow and system complexity increases, Rambus technologies help enable higher performance, greater efficiency, and stronger security across data centers, AI systems, networking infrastructure, and edge devices.​ This recognition is also a testament to the pe…

RISC-V Now! by Andes | Shanghai
type: item
date: 2026-03-25T21:25:02Z
description: We are excited to be participating at RISC-V Now! by Andes in Shanghai! Stay tuned to learn more. About RISC-V Now! RISC-V Now! is the conference focused on turning RISC-V standards into products that ship — where spec goes to scale. Built for Practitioners RISC-V Now! addresses the realities of moving from evaluation to production: […]
encoded: We are excited to be participating at RISC-V Now! by Andes in Shanghai! Stay tuned to learn more. About RISC-V Now! RISC-V Now! is the conference focused on turning RISC-V standards into products that ship — where spec goes to scale. Built for Practitioners RISC-V Now! addresses the realities of moving from evaluation to production: • System-level trade-offs in shipping AI and compute platforms • CPU and SoC strategy under power, cost, and scaling constraints • Software enablement challenges encountered in real deployments • Lessons learned—what worked, what didn’t, and what teams wish they had known earlier It brings together customers, ecosystem partners, and teams evaluating RISC-V for silicon, software, and system integration to share real-world experience deploying RISC-V at commercial scale. From AI and automotive to datacenter and IoT, RISC-V Now! goes beyond standards discussions to address the realities of execution: architecture decisions, software enablement, system integration, and business outcomes. To learn more, follow the link here: https://riscv.org/event/risc-v-now-by-andes-shanghai/

RISC-V Now! by Andes | Taiwan
type: item
date: 2026-03-25T21:22:15Z
description: We are excited to be participating at RISC-V Now! by Andes in Taiwan! Stop by booth #9 to learn more about our solutions. About RISC-V Now! RISC-V Now! is the conference focused on turning RISC-V standards into products that ship — where spec goes to scale. Built for Practitioners RISC-V Now! addresses the realities of […]
encoded: We are excited to be participating at RISC-V Now! by Andes in Taiwan! Stop by booth #9 to learn more about our solutions. About RISC-V Now! RISC-V Now! is the conference focused on turning RISC-V standards into products that ship — where spec goes to scale. Built for Practitioners RISC-V Now! addresses the realities of moving from evaluation to production: • System-level trade-offs in shipping AI and compute platforms • CPU and SoC strategy under power, cost, and scaling constraints • Software enablement challenges encountered in real deployments • Lessons learned—what worked, what didn’t, and what teams wish they had known earlier It brings together customers, ecosystem partners, and teams evaluating RISC-V for silicon, software, and system integration to share real-world experience deploying RISC-V at commercial scale. From AI and automotive to datacenter and IoT, RISC-V Now! goes beyond standards discussions to address the realities of execution: architecture decisions, software enablement, system integration, and business outcomes. To learn more, follow the link here: https://riscv.org/event/risc-v-now-by-andes-hsinchu/