At Rambus, we create cutting-edge semiconductor and IP products, providing industry-leading chips and silicon IP to make data faster and safer.
We are excited to be attending COMPUTEX in Taipei, Taiwan! If you would like to schedule some time to meet with us at the show, please send us an email here or fill out our contact form here. To register and learn more about COMPUTEX, visit the page here: https://www.computextaipei.com.tw/en/index.html About COMPUTEX Established in […]
We are excited to be attending COMPUTEX in Taipei, Taiwan! If you would like to schedule some time to meet with us at the show, please send us an email here or fill out our contact form here. To register and learn more about COMPUTEX, visit the page here: https://www.computextaipei.com.tw/en/index.html About COMPUTEX Established in 1981, COMPUTEX TAIPEI (also called COMPUTEX) is the leading global ICT and IoT show with a complete supply chain and ecosystems. Co-organized by the Taiwan External Trade Development Council (TAITRA) and Taipei Computer Association (TCA), COMPUTEX, based upon Taiwan’s complete ICT clusters, covers the whole spectrum of ICT industry, from established brands to startups and from ICT supply chain to IoT ecosystems. With strong R&D and manufacturing capabilities and IPR protection, Taiwan is a strategic destination for foreign companies and investors looking for partners in global technology ecosystems.
Live Webinar: HBM4E Advances ​Bandwidth Performance for AI Training
AI training continues to push the limits of memory bandwidth, latency, and system scalability. As model sizes grow and compute density increases, memory architecture has become a defining factor in overall system performance. HBM has emerged as the memory of choice for these workloads, and HBM4E represents the next major step forward. HBM4E extends the […]
AI training continues to push the limits of memory bandwidth, latency, and system scalability. As model sizes grow and compute density increases, memory architecture has become a defining factor in overall system performance. HBM has emerged as the memory of choice for these workloads, and HBM4E represents the next major step forward. HBM4E extends the HBM roadmap to address these challenges, delivering the performance headroom required for next-generation AI and HPC platforms. Join Rambus for a technical deep dive into HBM4E and the industry-leading HBM4E Memory Controller IP. In this webinar, Nidish Kamath from Rambus will walk through the key requirements driving HBM4E adoption and introduce Rambus’ newly announced HBM4E Memory Controller IP. The session will cover how HBM4E enables higher bandwidth, improved efficiency, and scalable integration for next-generation AI accelerators, along with practical considerations for building high-performance memory subsystems. We will explore why HBM4E is ideally suited for AI training, and what system architects should consider when deploying HBM4E in advanced AI designs.
Join us at D&R IP SoC Silicon Valley! Stop by Table 1 and chat with our experts about our Silicon IP offerings. We will also be presenting on three topics. Session information below. From Monolithic SoCs to Chiplets: A new Hardware Security Paradigm Speaker: Berardino Carnevale, Senior Technical Marketing and Product Manager at Rambus Abstract: […]
Join us at D&R IP SoC Silicon Valley! Stop by Table 1 and chat with our experts about our Silicon IP offerings. We will also be presenting on three topics. Session information below. From Monolithic SoCs to Chiplets: A new Hardware Security Paradigm Speaker: Berardino Carnevale, Senior Technical Marketing and Product Manager at Rambus Abstract: Chiplet‑based architectures are transforming SoC design, but they also upend long‑standing security assumptions. By disaggregating a monolithic die into multiple, often multi‑vendor chiplets, the implicit silicon trust boundary disappears, expanding the attack surface to include chiplet substitution, weak‑chiplet compromise, and exposed die‑to‑die interconnects. This presentation explores why traditional SoC security models fail in chiplet systems and introduces a system‑level security paradigm based on distributed trust with centralized authority. AI Inference needs a mix-and-match memory strategy Speaker: Nidish Kamath, Director of Product Management, Silicon IP at Rambus Abstract: AI inference spans diverse workloads, from low‑latency chat to long‑context reasoning and large‑scale recommendations—making single, monolithic accelerator and memory designs increasingly inefficient. This talk explains how inference naturally splits into prefill and decode stages with fundamentally different bottlenecks: prefill is compute‑bound, while decode is dominated by memory bandwidth and latency. By matching memory technologies to each stage, using cost‑efficient GDDR or LPDDR for prefill and reserving premium HBM for decode, with pooled memory for KV offload, operators can significantly reduce cost per token without sacrificing latency. The session outlines emerging disaggregated architectures for AI inference workloads. Enabling Efficient Edge AI Inferencing Through Ecosystem Collaboration Speakers: Nidish Kamath, Director of Product Management, Silicon IP at Rambus & Kevin Yee, Sr. Director of IP and Ecosystem Marketing, Samsung Foundry Abstract: As artificial intelligence continues to move from centralized data centers to the edge, delivering real‑time inferencing under strict power, performance, and area constraints has become a defining challenge for next‑generation systems. Meeting this challenge requires more than isolated innovation—it demands deep collaboration across AI compute architectures, memory subsystems, and advanced semiconductor process technologies. This presentation highlights a strategic collaboration between Rambus, and Samsung Foundry that exemplifies how ecosystem alignment can unlock efficient, scalable edge AI platforms. The session will explore how ultra‑efficient AI inference processors are combined with Rambus’ silicon‑proven LPDDR5/LPDDR5X memory controller IP and Samsung Foundry’s leading‑edge logic process technologies to enable high‑performance, low‑power AI inferencing across a wide range of edge applications, including robotics, smart cameras, industrial automation, and edge servers.
We’re excited to be participating at TSMC North America Technology Symposium! Stop by booth #400 and learn about our solutions. To learn more and register, click the link here: https://www.tsmc.com/static/english/campaign/Symposium2026/index.htm
Hardware Deployment for Secure AI Using Confidential Computing
AI’s fast evolution is producing autonomous systems that can operate with minimal human oversight, improve themselves and become effective at decision-making in complex environments. These developments require careful consideration of security and privacy. To limit the overhead performance impact (area, throughput, latency and power), hardware-based security solutions can be deployed using state-of-the-art silicon IP.
HBM4E Advances ​Bandwidth Performance for AI Training
[Live on April 8 at 11am PT] Join Rambus for a technical deep dive into HBM4E and the industry-leading HBM4E Memory Controller IP. In this webinar, Nidish Kamath from Rambus will walk through the key requirements driving HBM4E adoption and introduce Rambus’ newly announced HBM4E Memory Controller IP.
This tutorial will describe DRAM architecture in detail, highlighting the similarities and differences between different DRAM technologies and the unique tradeoffs and design choices made to meet system needs. We will also cover the key components that memory transactions travel thorough to get to DRAMs and back, including memory controllers, PHYs, and where applicable, modules and buffer chips. We will describe the architecture of these critical components and discuss how DRAM architecture choices impact their performance and power efficiency. Standard scaling techniques for DRAMs will be highlighted along with challenges that the industry is currently facing. Input from industry experts will show the pros and cons of DRAM architecture choices, demonstrating the system impact and requirements for mainstream adoption. Future DRAM architectures will also be discussed.
Scaling DRAM Technology to Meet Future Demands: System Challenges and Opportunities Saturday, June 27, 2026, Raleigh, North Carolina Full-Day tutorial held in conjunction with ISCA 2026 Home Tutorial Abstract Since the invention of the 1T1C bit cell more than 50 years ago, DRAMs have become the main memory of choice for processors in computing systems and consumer electronics devices. As new computing paradigms have been created, including AI, 3D graphics, HPC, cloud computing, and smart phones, specialized processors and DRAM memories have been developed that are optimized for these use cases. The same 1T1C DRAM bit cell is used in each of these applications, but the internal architecture and interfaces of the DRAMs supporting these markets are optimized in different ways, and the DRAMs are packaged differently (sometimes with additional buffer chips) to meet the needs of the system. Across all markets, there is a relentless demand for higher performance and better power efficiency, as insufficient DRAM bandwidth can bottleneck application performance and interfaces to DRAMs can consume half of the SOC power. DRAMs are also being stressed by growing reliability concerns as they incorporate on-die ECC and mitigation for disturbance effects such as RowHammer and RowPress. As AI continues to grow across markets (HPC, server, client, mobile, etc.), the design of efficient, performant and reliable memory systems is becoming increasingly critical. AI models are continuing to grow, pushing the capacity and bandwidth requirements of DRAMs. Simply scaling with historical techniques will no longer achieve the required characteristics due to physical challenges, limits of process scaling, and system architecture constraints including thermals and power delivery. This tutorial will describe DRAM architecture in detail, highlighting the similarities and differences between different DRAM technologies and the unique tradeoffs and design choices made to meet system needs. We will also cover the key components that memory transactions travel thorough to get to DRAMs and back, including memory controllers, PHYs, and where applicable, modules and buffer chips. We will describe the architecture of these critical components and discuss how DRAM architecture choices impact their performance and power efficiency. Standard scaling techniques for DRAMs will be highlighted along with challenges that the industry is currently facing. Input from industry experts will show the pros and cons of DRAM architecture choices, demonstrating the system impact and requirements for mainstream adoption. Future DRAM architectures will also be discussed. Topics that will be covered The tutorial will focus on DRAM architecture, specifically looking at design tradeoffs and subsequent impact to the overall system performance, power, cost and reliability. The tutorial will cover the following topics: Background and History of DRAM markets. How they were historically defined, what changed, and the drivers of new technologies. DRAM array architecture, internal data paths, shared structures, and interfaces. The future of DRAM, including 3D DRAM cells. Memory modules, including DIMMs, CAMMs, MRDIMMs, and CXL modules and their buffer chips. Capacity, power, reliability, cost tradeoffs that motivate different DRAM architectures for different markets including computing, mobile, graphics, and AI. This will include underlying core architecture, packaging and system integration. Power and energy differences between DRAM technologies. Novel packaging techniques including stacking and 2.5D assembly. Reliability, Availability, and Serviceability (RAS) techniques, including on-die error correction, system-level ECC, redundancy and repair, and RowHammer and RowPress mitigation. Processing in memory that has been implemented in DRAM silicon. Memory controller architecture and design challenges with current and future DRAMs. PHY architectures and challenges with achieving higher data rates and power efficiencies. System performance considerations, including latency under load and the impact of core timings and core architecture on performance. Memory system architecture considerations to achieve maximum performance, highlighting the impact of DRAM core timing and architecture tradeoffs on the host controller design. Industry adoption challenges facing new DRAM technologies and features. Challenges for the future. Organizers and Affiliations Steven Woo is a Fellow and Distinguished Inventor at Rambus Inc., where he leads research in Rambus Labs on advanced memory systems for accelerators and computing infrastructure, and manages a team of senior architects. Since joining Rambus, Steve has worked in various roles leading architecture, technology, and performance analysis efforts, and in marketing and product planning roles leading strategy and customer programs. He has more than 30 years of experience working on advanced memory systems and holds more than 100 US and international patents. Steve received his PhD and MS degrees in Electrical Engineering from Stanford University, and Master of Engineering and BS Engineering degrees from Harvey Mudd College. Wendy Elsasser is a Technical Director of Research Science at Rambus Inc. She works in the Rambus Labs R&D division researching future system architecture and developing innovative solutions to address the challenges of the memory sub-system. She has over 25 years of experience in industry, starting with semi-custom micro-controller design, test, and implementation. Over the last 20 years, her focus has been on memory sub-systems, primarily external DRAM. Her experience includes DRAM controller architecture, design, and validation as well as active contributions to consortiums and standards bodies. Specifically, she was a leader in the Gen-Z consortium and JEDEC, helping to define future memory interfaces and DRAM standards. Her work has resulted in 15 patents. Robert Palmer is a Senior Technical Director of Research Science at Rambus Inc., leading research in future memory module and memory bu􀆯er chip architectures. He has over 25 years of industry experience developing silicon IP and communication ICs, spanning the design of high-speed wireline transceiver circuits, serial link and memory controller PHY microarchitectures, and DDR and CXL memory bu􀆯er chip architectures and microarchitectures. In addition to his tenure at Rambus, Robert has held positions at Velio Communications and Nvidia Research. He holds over 60 US and international patents. Taeksang Song is a Corporate Vice President at Samsung Electronics where he is leading a team dedicated to pioneering cutting-edge technologies including CAMM, MRDIMM, CXL memory expanders, fabric attached memory solutions and processing near memory to meet the evolving demands of next-generation data-centric AI architectures. He has 20 years of professional experience in memory and sub-system architecture, interconnect protocols, system-on-chip design and collaborating with CSPs to enable heterogeneous computing infrastructure. Prior to joining Samsung Electronics, he worked at Rambus Inc., Micron Technology and SK hynix in lead architect roles for the emerging memory controllers and systems. Taeksang received his PhD from KAIST, South Korea, in 2006. He has authored and co-authored over 20 technical papers and holds over 50 U.S. patents.
Download the product to learn about the Rambus HBM4E Controller. Our HBM4E Controller is designed to support customers with deploying a new generation of HBM memory for cutting-edge AI accelerators, graphics and high-performance computing (HPC) applications.
Rambus offers the industry’s fastest HBM4E Controller IP core designed to support customers with deploying a new generation of HBM memory for cutting-edge AI accelerators, graphics and high-performance computing (HPC) applications.
HBM4E Controller IP Contact Us Home Rambus offers the industry’s fastest HBM4E Controller IP core designed to support customers with deploying a new generation of HBM memory for cutting-edge AI accelerators, graphics and high-performance computing (HPC) applications. Secure Site Login Contact Product Brief How the Rambus HBM4E Controller Works The core accepts commands using a simple local interface and translates them to the command sequences required by HBM4/4E devices. The core also performs all initialization, refresh and power-down functions. The core queues up multiple commands in the command queue. This enables optimal bandwidth utilization for both short transfers to highly random address locations as well as longer transfers to contiguous address space. The command queue is also used to opportunistically perform look-ahead activates, precharges and auto-precharges, further improving overall throughput. The Reorder functionality is fully integrated into the controller command queue increasing throughput and minimizing gate count. <img fetchpriority="high" decoding="async" width="972" height="574" src="https://www.rambus.com/wp-content/uploads/2026/03/HBM4E_Controller_IP_Block_Diagram.png" class="attachment-full size-full wp-image-66087" alt="HBM4E Memory Subsystem" srcset="https://www.rambus.com/wp-content/uploads/2026/03/HBM4E_Controller_IP_Block_Diagram.png 972w, https://www.rambus.com/wp-content/uploads/2026/03/HBM4E_Controller_IP_Block_Diagram-300x177.png 300w, https://www.rambus.com/wp-content/uploads/2026/03/HBM4E_Controller_IP_Block_Diagram-150x89.png 150w, https://www.rambus.com/wp-content/uploads/2026/03/HBM4E_Controller_IP_Block_Diagram-768x454.png 768w" sizes="(max-width: 972px) 100vw, 972px" /> HBM4E Memory Subsystem The controller can be delivered standalone or integrated with the customer’s choice of HBM4E PHY to instantiate a complete HBM4E memory subsystem. Ask the Experts: HBM4 Controller IP In this episode of Ask the Experts, we discuss HBM4 with Nidish Kamath, director of product management for memory interface IP at Rambus. Topics discussed include: how AI is influencing the development of the HBM specification, what we know so far about HBM4, the implementation challenges associated with HBM4, the Rambus HBM4 Controller IP offering, and why customers should choose Rambus for their HBM designs. Solution Offerings Features Deliverables Services Features Supports HBM4/4E memory devices Supports all standard HBM4 channel densities (up to 32 Gb) Supports up to 16 Gbps/pin Refresh Management (RFM) support Maximize memory bandwidth and minimizes latency via Look-Ahead command processing Integrated Reorder functionality Achieves high clock rates with minimal routing constraints Self-refresh and Power-down Low Power Modes Support for HBM4 RAS features Built-in hardware-level performance Activity Monitor DFI compatible End-to-end data parity Support AXI, CHI or native interface to user logic Deliverables Core (source code) Testbench (source code) Complete documentation Expert technical support Maintenance updates Services Engineering Design Services: Customization SoC Integration Protocol Compatibility Protocol Data Rate (Gbps) Max. Application HBM4E 16 AI/ML, HPC, Graphics From the blog <div class="elementor-element elementor-element-066523d elementor-grid-3 elementor-grid-tablet-2 elementor-grid-mobile-1 elementor-posts--thumbnail-top elementor-card-shadow-yes elementor-posts__hover-gradient elementor-widget elementor-widget-posts" data-id="066523d" data-element_type="widget" data-e-type="widget" data-settings="{"cards_columns":"3","cards_columns_tablet":"2","cards_columns_mobile":"1","cards_row_gap":{"unit":"px","size":35,"sizes":[]},"cards_row_gap_tablet":{"unit":"px","size":"","sizes":[]},"cards_row_gap_mobile":{"unit":"px","size":"","sizes":[]}}" data-widget_type="posts.cards"> <img decoding="async" width="800" height="603" src="https://www.rambus.com/wp-content/uploads/2024/06/HBM-Everything-You-Need-to-Know.jpg" class="attachment-full size-full wp-image-65842" alt="HBM: Everything You Need to Know" srcset="https://www.rambus.com/wp-content/uploads/2024/06/HBM-Everything-You-Need-to-Know.jpg 800w, https://www.rambus.com/wp-content/uploads/2024/06/HBM-Everything-You-Need-to-Know-300x226.jpg 300w, https://www.rambus.com/wp-content/uploads/2024/06/HBM-Everything-You-Need-to-Know-150x113.jpg 150w, https://www.rambus.com/wp-content/uploads/2024/06/HBM-Everything-You-Need-to-Know-768x579.jpg 768w" sizes="(max-width: 800px) 100vw, 800px" /> High Bandwidth Memory (HBM): Everything You Need to Know <img decoding="async" width="500" height="286" src="https://www.rambus.com/wp-content/uploads/2026/02/ai-edge-blog.jpg" class="attachment-full size-full wp-image-66028" alt="AI on Chip" srcset="https://www.rambus.com/wp-content/uploads/2026/02/ai-edge-blog.jpg 500w, https://www.rambus.com/wp-content/uploads/2026/02/ai-edge-blog-300x172.jpg 300w, https://www.rambus.com/wp-content/uploads/2026/02/ai-edge-blog-150x86.jpg 150w" sizes="(max-width: 500px) 100vw, 500px" /> DEEPX, Rambus, and Samsung Foundry Collaborate to Enable Efficient Edge Inferencing Applications <img loading="lazy" decoding="async" width="800" height="450" src="https://www.rambus.com/wp-content/uploads/2025/11/bae-press-release-1.jpg" class="attachment-full size-full wp-image-65900" alt="Silicon IP for the Final Frontier" srcset="https://www.rambus.com/wp-content/uploads/2025/11/bae-press-release-1.jpg 800w, https://www.rambus.com/wp-content/uploads/2025/11/bae-press-release-1-300x169.jpg 300w, https://www.rambus.com/wp-content/uploads/2025/11/bae-press-release-1-150x84.jpg 150w, https://www.rambus.com/wp-content/uploads/2025/11/bae-press-release-1-768x432.jpg 768w" sizes="(max-width: 800px) 100vw, 800px" /> Silicon IP for the Final Frontier News <div class="elementor-element elementor-element-5738453 elementor-grid-1 elementor-posts--thumbnail-none elementor-grid-tablet-2 elementor-grid-mobile-1 elementor-widget elementor-widget-posts" data-id="5738453" data-element_type="widget" data-e-type="widget" data-settings="{"classic_columns":"1","classic_row_gap":{"unit":"px","size":7,"sizes":[]},"classic_columns_tablet":"2","classic_columns_mobile":"1","classic_row_gap_tablet":{"unit":"px","size":"","sizes":[]},"classic_row_gap_mobile":{"unit":"px","size":"","sizes":[]}}" data-widget_type="posts.classic"> Rambus Sets New Benchmark for AI Memory Performance with Industry-Leading HBM4E Controller IP Rambus Announces Industry-First HBM4 Controller IP to Accelerate Next-Generation AI Workloads Rambus Boosts AI Performance with 9.6 Gbps HBM3 Memory Controller IP Papers <div class="elementor-element elementor-element-0abc315 elementor-grid-1 elementor-posts--thumbnail-none elementor-grid-tablet-2 elementor-grid-mobile-1 elementor-widget elementor-widget-posts" data-id="0abc315" data-element_type="widget" data-e-type="widget" data-settings="{"classic_columns":"1","classic_row_gap":{"unit":"px","size":7,"sizes":[]},"classic_columns_tablet":"2","classic_columns_mobile":"1","classic_row_gap_tablet":{"unit":"px","size":"","sizes":[]},"classic_row_gap_mobile":{"unit":"px","size":"","sizes":[]}}" data-widget_type="posts.classic"> HBM4E Memory: Break Through to Greater Bandwidth MIPI DSI-2 & VESA Video Compression Drive Performance for Next-Generation Displays Supercharging AI Inference with GDDR7 Webinars <div class="elementor-element elementor-element-c363dd2 elementor-grid-1 elementor-posts--thumbnail-none elementor-grid-tablet-2 elementor-grid-mobile-1 elementor-widget elementor-widget-posts" data-id="c363dd2" data-element_type="widget" data-e-type="widget" data-settings="{"classic_columns":"1","classic_row_gap":{"unit":"px","size":7,"sizes":[]},"classic_columns_tablet":"2","classic_columns_mobile":"1","classic_row_gap_tablet":{"unit":"px","size":"","sizes":[]},"classic_row_gap_mobile":{"unit":"px","size":"","sizes":[]}}" data-widget_type="posts.classic"> HBM4E Memory: Break Through to Greater Bandwidth MIPI DSI-2 & VESA Video Compression Drive Performance for Next-Generation Displays Supercharging AI Inference with GDDR7 Contact Us Related Markets & Applications <defs> </defs><circle class="cls-1" cx="51.22" cy="51.22" r="51.22"></circle><path class="cls-2" d="M84.39,47.86l-22-22a4.13,4.13,0,1,0-5.83,5.84h0l15.06,15-49.43.05a4.13,4.13,0,0,0,0,8.25h0L71.4,55,56.69,69.74a4.12,4.12,0,0,0,5.83,5.82L84.39,53.69A4.12,4.12,0,0,0,84.39,47.86Z"></path> AI & Machine Learning <defs> </defs><circle class="cls-1" cx="51.22" cy="51.22" r="51.22"></circle><path class="cls-2" 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