News
Rambus Reaches 1,000th Patent Milestone
07/15/2010
07/15/2010
Presented by Rambus Fellow Craig Hampel at the 2010 Multicore Expo, this presentation addresses memory architecture optimizations that can support the many threads and workloads handled by multi-core processors in next-generation PCs and smartphones.
Presented by Rambus technical director, Jared Zerbe, at the IEEE 2010 Symposium on VLSI Circuits, this paper discusses the design of a low-power 5Gb/s signaling system using a new clock/data skew minimization technique with a source-synchronous transmit clock delay line and integrating receiver.
The world's fastest and most power-efficient memory for mobile applications
Harnessing the advantages of LEDs for affordable and energy-efficient general lighting