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File Name: A 14-mW 6.25-Gb/s Transceiver in 90-nm CMOS

This paper describes a 6.25-Gb/s 14-mW transceiver in 90-nm CMOS for chip-to-chip applications. The transceiver employs a number of features for reducing power consumption, including a shared LC-PLL clock multiplier, an inductor-loaded resonant clock distribution network, a low- and programmable-swing voltage-mode transmitter, software-controlled clock and data recovery (CDR) and adaptive equalization within the receiver, and a novel PLL-based phase rotator for the CDR. The design can operate with channel attenuation of -15 dB or greater at a bit-error rate of 10-15 or less, while consuming less than 2.25 mW/Gb/s per transceiver.

This paper appears in the December 2007 issue of "IEEE Journal of Solid-State Circuits" and is available for purchase on the IEEE website.

At ISSCC 2009, Rambus was presented with the 2007 Journal of Solid-State Circuits Best Paper Award for this paper.

Online Resource: IEEE
Resource URL: http://ieeexplore.ieee.org

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