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The Rambus Media Library is a collection of videos, presentations, and technical papers. To get started, enter a topic to search on (such as "XDR2" or "mobile") below. You can also refine your search by a specific technology, event, or year. For example, if you wanted a paper that was presented at DesignCon 2009, you would select "Any Technology," "DesignCon," and "2009."
Results 1 - 10 of 36 total results for "*"
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DDR3 SDRAM is being used in many computing systems today and offers data rates of up to 1600Mbps. To achieve performance levels beyond DDR3, future main memory subsystems must attain faster data rates while maintaining low power, access ...
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A 5Gb/s signaling system was designed and fabricated in TSMC’s 40nm LP CMOS process. A new clock/data skew minimization technique with a source-synchronous transmit clock delay line and integrating receiver tolerates high frequency...
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Rambus collaborated with IBM and Xilinx to establish a high-bandwidth interface between an IBM Power Processor and the latest Xilinx FPGAs via Rambus' FlexIO™ processor bus interface. Read this application note to learn more.
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Simultaneous switching noise is a major performance limiter for single-ended signaling systems as data rates scale higher. This paper presents a methodology to analyze the performance of single-ended interface systems like GDDR3 in the ...
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In contrast to most chip-to-chip I/O interfaces that use differential signaling, the mainstream memory interface designs are based on single-ended signaling such as SSTL or PODL. Extending the data rate for single-ended signaling beyond ...
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There is a general consensus that 10 Gbps copper backplane serial links will be deployed in the near future. This paper takes a look at the practical and cost effective design aspects of the 10-12.5 Gbps links as well as the feasibility ...
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This paper describes the modeling of power supply noise in a high-bandwidth XDR™ DRAM memory system and the correlation with measurement results in time domain while the system is operating. A supply network model is presented that ...
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Mixed-signal integration is the verification step that ensures a combination of digital and analog blocks operates correctly as a system. While mixed-signal simulation can be part of the process, it is important to understand the ...
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This paper presents a systematic approach for analyzing supply noise induced timing jitter in high-speed I/O interfaces. The proposed method combines frequency-dependent supply noise jitter sensitivity profile with supply noise spectral ...
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The performance of mutli-gighertz interconnect systems is adversely impacted by non-ideal physical effects such as attenuation, crosstalk, impedance mismatches, inter-symbol interference, and by parameter variations due to process and ...
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