Search the Media Library
The Rambus Media Library is a collection of videos, presentations, and technical papers. To get started, enter a topic to search on (such as "XDR 2" or "mobile") below. You can also refine your search by a specific technology, event, or year. For example, if you wanted a paper that was presented at DesignCon 2010, you would select "Any Technology," "DesignCon," and "2010."
Results 1 - 10 of 32 total results for "*"
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The Rambus XDR™ memory architecture achieves an order of magnitude higher performance than today's standard memories with the fewest ICs. XDR DRAM powers today's best consumer electronic devices, including the Sony Playstation®3.
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Rambus Senior Engineering Manager Arun Vaidyanath demonstrates the latest Rambus test chip running in 3 modes: high-speed differential, GDDR5, and DDR3. Groundbreaking memory technologies developed by Rambus enable signaling at 20...
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The Mobile XDR™ memory architecture is the world's fastest and most power-efficient memory for mobile applications. Capable of achieving data rates of 3.2 to 4.3 Gigabits per second (Gbps) per pin at an unprecedented power efficiency of ...
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Join us for an inspirational look at Rambus' 20-year commitment to innovation. Featuring Mike Farmwald and Mark Horowitz, Rambus founders, and former CEO Harold Hughes.
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The making of our stop-motion TV commercial
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Rambus' TV ad based on stop-motion animation
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Every year Rambus employees are given the opportunity to join thousands of volunteers across the country to participate in National Rebuilding Day. Rebuilding Together matches families in need with groups of volunteers to repair and...
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See the demo of a silicon-proven XDR™2 board achieving the industry's highest memory bandwidth. Rob Dhat, Solutions Marketing Manager, walks through the advantages of XDR 2 DRAM over GDDR5.
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Rambus supports the KISS Institute's Botball Educational Robotics Program which engages middle and high school aged students in a team-oriented robotics competition based on national science education standards.
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Rambus innovations enable our DDR3 PHY solution to support data rates of up to 1600 megatransfers per second (MT/s) in a low-cost wire bond package. Watch this video to see the test chip in action.
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