The Rambus Mobile XDR™ architecture incorporates innovations first developed as part of the Mobile Memory Initiative. The innovations that enable the high bandwidth and low power of the Mobile XDR memory architecture include:
Very Low-Swing Differential Signaling (VLSD) combines the robust signaling qualities of a differential architecture with innovative circuit techniques to greatly reduce active power consumption. Using a ground reference voltage mode driver, VLSD enables data rates of up to 4.3Gbps with only a 200mV peak-to-peak differential voltage swing and a common mode of 100mV.
FlexClocking™ Architecture is a topology where the clock is forwarded and distributed to both the controller and the DRAM device from a central PLL. Using Rambus FlexPhase™ technology to adjust for any variability between the clock and DQ signals, the FlexClocking Architecture enables high-speed operation without the need for a DLL or PLL on the DRAM device. This simplifies DRAM design and reduces power consumption.
Advanced Power State Management (APSM) builds on the FlexClocking architecture and innovative circuit design techniques. APSM reduces memory system power, optimizes power efficiency across operating modes, and provides ultra-fast transition times between various low-power and active operating modes.
In addition to VLSD, FlexClocking architecture, and APSM, the Mobile XDR architecture features the following Rambus innovations:
Micro-threading Technology - reduces row and column access granularity resulting in a significant performance benefit for applications dealing with small data objects.
FlexLink™ C/A - provides the command and address information to a DRAM using a single, differential high speed communications channel.
