Beyond DDR4: R+™ Technologies to Advance Main Memory

Created as part of the R+ Enhanced Standard Solutions, Rambus has developed a set of inventions focused on advancing single-ended signaling technologies to meet the memory system requirements of next-generation computing applications while maintaining compatibility with current industry standard DDR4 solutions. These inventions have been proven in silicon, and deliver compelling performance and power efficiency benefits that allow customers to differentiate their future-generation computing products.

This next-generation R+ main memory architecture advances single-ended signaling up to 6.4 gigabits per second (Gbps) in a multi-rank, multi-DIMM system. Built upon Rambus inventions such as FlexPhase™ circuitry, Dynamic Point-to-Point, Near Ground Signaling, Module Threading, and Ultra-Fast Power-On technology, this R+ architecture can achieve up to twice the data rates of current DDR4 DRAMs while improving the power efficiency by up to 55%.

How it works

Improved Performance

Near Ground Signaling, an innovative single-ended, ground-terminated signaling technology, enables data rates of up to 6.4Gbps,which is twice the data rates of DDR4 DRAMs in standard PC and server platforms. Module Threading and DRAM multi-threading capabilities ensure high sustained bandwidth for future many-core CPUs in addition to the high peak bandwidth achievable with the fast signaling.

To provide for capacity expansion, Dynamic Point-to-Point Topology ensures that all memory bus signals between the CPU and the DRAMs are always point-to-point independent of the number of populated memory slots. This enables the memory bus to run at the maximum data rate when fully populated, unlike current systems where memory bus speed decreases as more DIMM slots are populated.

Reduced Power

Asymmetrical memory system architecture enables aggressive and granular power management of agile DRAMs by placing all complex timing circuits like PLLs and DLLs in the memory controller. The DRAMs dissipate negligible I/O power in standby mode since the I/O circuits are OFF at all times except during a read or write operation, resulting in up to 55% higher power efficiency than current DRAMs.

Cost-Effective

Maximum re-use of existing infrastructure like connectors and high-volume PCB technology greatly reduces system cost and facilitates rapid adoption. This simplifies the DRAM design, increasing yield while reducing test costs.

The Motivation

Demand for an enriched end-user experience and increased performance in next-generation mainstream computing applications is unremitting. Driven by multi-core computing, virtualization and processor integration trends, the industry needs a next-generation main memory solution capable of achieving data rates of up to 6400Mbps in the same, or lower power envelope as current DDR4 memory solutions. The divergence of these two requirements, increasing performance while lowering power, presents a difficult challenge for future memory system designers.

In addition, next-generation memory solutions face potential bottlenecks in access efficiency and capacity, both of which have fallen as date rates increased. Memory module upgrades are the most common way to increase capacity in a system. The number of modules supported on a DDR4 memory channel drops at high data rates due to degraded signal integrity. This problem has led to a change in topology from multiple DIMMs per memory channel to a point-topoint topology that only supports a single DIMM per memory channel. This makes a DDR4 memory system difficult to scale and non-ideal for most server, workstation and high-end PCs. Memory access granularity also suffers as data rates increase due to the disparity between the interface and core access speeds. The result is an increase to the core prefetch and a sub-optimal transfer size for future multi-core and graphics computing applications.

The R+ technologies for extending main memory address these issues by enabling single-ended signaling to go beyond DDR4 in a power-efficient and cost-effective manner.