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Advanced Power State Management (APSM)
Summary
Mobile devices and their associated applications are “bursty” in nature. In order to provide superior performance and optimal power efficiency across all operating modes requires a mobile memory architecture that is capable of switching quickly between active and idle (or power down) states and back again.
Building on the FlexClocking™ Architecture and innovative techniques such as clock pausing, Advanced Power State Management (APSM) reduces memory system power and provides ultra-fast transition times between various low-power and active operating modes.
Clock power is saved by synchronously “pausing” the clock distribution at its root which cleanly turns off clocks to circuitry in both the controller and the DRAM. As shown in the figure below, the root of the distribution circuitry is located at the output of the clock multiplier located in the PLL block.
The design supports three low-power states and one active state which are responsive to command traffic from the memory controller. These states are described in the table below:
| P1 - Deep Power Down | Only leakage power is consumed. |
| P2 - Power Down | Only the clock multiplier is turned on. |
| P3 - Idle | The clock distribution is paused. |
| P4 - Active | The memory controller interface and DRAM interface are active. |
Commercial and Performance Benefits
- APSM enables quick turn-off and transition into low-power modes to conserve power.
- APSM enables quick transition from low-power modes to active mode to maximize system responsiveness.
- APSM delivers optimized power consumption for all usage profiles.
APSM is an element of the Rambus Mobile Memory initiative. The Mobile Memory initiative is driving the development of signaling technologies needed for future mobile memory architectures capable of delivering over 17GB/s of memory bandwidth with best-in-class power efficiency from a single DRAM device.