Core Prefetch

Background

Rapid advances in CPU clock speeds and architectural techniques such as pipelining and multithreading have placed increasing demands on memory system bandwidth with each new generation of computer systems. As the processor-memory performance gap continues to grow, succeeding generations of computer systems will increasingly become limited by their memory systems, in particular by memory system bandwidth. This problem was evident in the late 1980s and became much more prominent in the 1990s.

Providing high memory bandwidth is a challenging problem, and doing so within the constraints of high-yield, high-volume manufacturing adds to this challenge. A key aspect of increasing memory system bandwidth is boosting the rate of data transfer between the DRAM interface and the DRAM core where data is stored. In the early 1990s, an important innovation that Rambus developed - core prefetch - allowed this data transfer rate to increase. Core prefetch lowers the cost of providing high bandwidth and supplies headroom for further bandwidth improvements.

What Is Core Prefetch?

A fundamental problem with increasing DRAM bandwidth is increasing the data transfer rate between the DRAM interface and the DRAM core. One possibility is to increase the frequency of the DRAM core to match that of the DRAM interface. However, this introduces additional circuit complexity, increases die size, and raises DRAM power consumption, resulting in higher manufacturing cost and lower yield. Core prefetch takes a different approach to solving this problem by allowing the DRAM core to run at a reduced speed compared to the DRAM interface. To match the bandwidth of the interface, each core access transfers multiple bits of data from the core to make up for this difference in transfer speeds. In this manner, core prefetch lets DRAM bandwidth increase, even if the DRAM core is limited to operating at a lower speed.

Figure 3 illustrates that core prefetch has become a widely adopted method for improving interface signaling rates of modern DRAMs; this preserves high-volume manufacturability of these products by leveraging lower-speed, high-yield DRAM cores. The first Rambus DRAMs manufactured in the early 1990s incorporated 8n core prefetch, which allowed the interface to transfer data at 8 times the speed of the DRAM core, for an effective transfer speed of 500 MHz. XDR DRAMs increase core prefetch to 16n. The latest generation of synchronous DRAMs does not use core prefetch, resulting in an interface transfer speed equal to the core transfer speed. More recently, other types of DRAMs, such as DDR and DDR2, have incorporated core prefetch to increase interface bandwidth while leveraging lower-speed cores. DDR DRAMs use 2n core prefetch, while DDR2 DRAMs use 4n core prefetch.

Who Benefits?

By lowering the cost to achieve high DRAM bandwidths, core prefetch benefits many different groups, including:

• DRAM manufacturers: Higher yields brought about by running the core at a lower speed increase the saleable number of DRAMs in a manufacturing run.
• Controller designers: Being able to supply a given level of bandwidth with fewer DRAMs reduces controller pin count and package cost.
• System integrators: Supplying a given level of bandwidth while minimizing the number of DRAMs decreases bill of materials costs and allows smaller form factors in some systems.
• Consumers: Lower system cost can be achieved thanks to higher DRAM yields, reduced package costs, and fewer DRAMs needed in the system.