Double Bus Rate Technology

Background

In many computing systems today, memory bandwidth is a key factor in determining overall system performance, and its importance continues to grow as these systems evolve. Rambus developed a technique for improving memory system bandwidth by increasing the per-pin signaling rate of the data pins of the DRAM. Double Data Rate (DDR) SDRAMs are an example of memory devices that double the per-pin data signaling rate by transferring data on both edges during each clock cycle instead of only on one edge. While such an increase in signaling rate can improve memory bandwidth of the data pins, actual system performance may not improve due to insufficient address/control bandwidth that can reduce data transfer efficiency. To address this problem, Rambus developed Double Bus Rate Technology, an innovation that increases both address/control, and data bandwidth, allowing memory systems to achieve higher levels of performance.

What Is Double Bus Rate Technology?

Figure 1 illustrates how increasing the per-pin data signaling rate of a DRAM increases the amount of memory bandwidth. The upper portion of Figure 1 shows the timing relationships between address and control information sent to the DRAM and data returning from the DRAM for a single memory Read transaction with a burst length of 4. This transaction transfers address, control, and data on one edge of each clock cycle to achieve single data rate transfers. The lower portion of Figure 1 shows how memory bandwidth can be increased by applying Double Bus Rate Technology to the data pins of the DRAMs. As the bottom half of Figure 1 shows, Double Bus Rate Technology allows data to be transferred more quickly, increasing the bandwidth that a DRAM can supply.

Figure 2 illustrates how doubling the rate of the data transfers affects the relationship between address/control information and data for a Read transaction. The bottom half of Figure 2 shows how double data rate transactions can be interleaved, and illustrates a problem that can occur when the amount of time that data occupies the memory bus is smaller than the amount of time that address and control information occupy the bus. In this situation, the insufficient address/control bandwidth leads to bubbles in the data transfer on the bus, resulting in reduced memory bandwidth and loss of performance.

The issue of performance loss illustrated in Figure 2 can be addressed by applying Double Bus Rate Technology to the address and control pins as well. Figure 3 illustrates how Double Bus Rate Technology is used to balance address, control, and data bandwidth, thereby eliminating the concerns relating to insufficient address and control bandwidth. As shown in the lower half of Figure 3, bandwidth is increased by 50% compared to the interleaved transactions shown in Figure 2. Another example of where increased control bandwidth can be useful is in systems that use write masking. In systems that utilize write masking, increasing the amount of data being transferred to memory requires that more byte masking control information be specified in order to maintain support for data masking at byte granularities. By balancing address, control, and data transfer rates on the bus with Double Bus Rate Technology, performance losses due to insufficient address and control bandwidth such as those shown in Figure 2 are eliminated.

Who Benefits?

Examples of some of the groups that benefit from Double Bus Rate Technology are:

• System designers. By balancing address, control, and data bandwidth, system designers are able to achieve the highest levels of memory bandwidth in their systems. This in turn helps to reduce the number of DRAMs necessary to achieve a given level of memory performance, reducing component count and easing system component placement, routing concerns, and thermal dissipation.
• System integrators. As for system designers, system integrators benefit from the reduced component count needed to achieve a given level of memory bandwidth, resulting in lower system cost and smaller form-factor systems.