Phase Interpolator Based CDR

Background

In order to communicate data from one chip to another across a signal line, the receiving chip must know when to sample the data signal that it receives from the transmitting chip. In many systems, this information is provided by a timing (clock) signal sent from the transmitting chip to the receiving chip along a dedicated timing signal line adjacent to the data signal line.

In systems with relatively low signaling rates, the receiving chip can directly use an internally buffered version of this timing signal to extract the data from the data signal. This is the method used in SDRAM technology. In systems with higher signaling rates, however, the receiving chip typically requires a clock alignment circuit, such as a Phase Locked Loop (PLL) or Delay Locked Loop (DLL). Such circuits create an internal sampling clock signal, precisely aligned with the received timing signal, to extract the data from the data signal. This is the method used in RDRAM and DDR technologies. Regardless of whether a clock alignment circuit is used, the data and timing lines must be well matched to eliminate timing skews between them which reduce a system's timing margin.

As data rates continue to increase, it is becoming increasingly difficult to match the data and timing signal lines to eliminate timing skews. Furthermore, requiring a timing signal line to be routed along with the data line(s) is costly in terms of board area and power. An attractive option is to remove the timing line and instead use a circuit on the receiving chip that requires only the data signal itself to determine when to sample the data signal to most reliably extract the data. Such a circuit is called a Clock-Data Recovery (CDR) circuit. Figure 1 shows example chip-to-chip connections with and without a timing signal line.

Although CDRs are typically designed using a modified PLL, such PLL-based CDRs are difficult to design, costly in terms of power and area, and suffer from several other limitations. For example, in designing a PLL-based CDR, the designer must compromise between the ability to track the data signal and noise suppression of the PLL. Additionally, the dynamics of PLL-based CDRs are dependant on the contents of the data signal, and PLL-based CDRs can have a long locking time since they must lock to both the frequency and phase of the data signal. PLL-based CDRs also suffer from analog offsets and device mismatches which can cause the receiver circuitry to sense the data signal at shifted, sub-optimal sampling points. Lastly, for chips receiving multiple data signals, a dedicated PLL-based CDR must be provided for each data signal. This is a costly requirement since these PLLs typically require relatively large silicon area (e.g. for large filter capacitors) and dissipate relatively large amounts of power (e.g. for various high speed PLL components).

What Is a Phase Interpolator Based CDR?

A phase interpolator based CDR is an alternative circuit architecture developed by Rambus which provides multiple advantages compared to PLL-based CDRs.

Figure 2 illustrates how phase interpolator based CDRs work and why they are advantageous compared to PLL-based CDRs. This type of CDR uses a PLL or DLL to implement a reference loop which accepts an input reference clock signal and produces a set of high speed clock signals, used as reference phases, spaced evenly across 360 degrees. These reference phases are then fed to a CDR loop which includes circuitry for selecting pairs of reference phases and interpolating between them to provide clocks for recovering the data from the data signal. Figure 3 illustrates an example of phase interpolation between two input signals of different phase to produce an output signal of intermediate phase.

Because of the separation between the reference loop and the CDR loop, the designer of a phase interpolator based CDR can separately optimize both the noise suppression of the reference loop and the tracking agility of the CDR loop. Additionally, the reference loop is not affected by the contents of the data signal, potentially allowing this type of CDR to track a wider variety of data signals. Furthermore, the relatively long locking time of the reference loop applies only at start-up when initially locking to the reference clock signal. After the initial locking time, interpolator-based CDRs can provide much faster re-locking compared to PLL-based CDRs whenever the data signal returns after being interrupted.

Another benefit of phase interpolator based CDRs is that the data sampling point can be precisely adjusted by a digitally controlled offset. This allows the cancellation of offsets from device mismatches and other causes, and enables in-system measurements of the timing margin available for reliably extracting data from the data signal.

Lastly, although the reference loop can occupy the majority of the area and dissipate the majority of the power in a phase interpolator based CDR, its reference phases can be shared among several CDR loops on chips receiving multiple data signals. In this way, the average size and power required for the CDR functionality per data signal can be greatly reduced.

Who Benefits?

The use of phase interpolator based CDRs benefits many different groups, including:

• ASIC vendors: By designing ASICs including Rambus I/O cells that utilize phase interpolator based CDRs, ASIC vendors benefit from the smaller area, lower power, and more stable operation of the I/O cells. These benefits are magnified when dual, quad, or other multi-lane I/O cells are used since these cells use one reference loop to drive multiple CDR loops for implementing multiple CDRs. The area and power savings can be significant compared to using a PLL per lane, as required by other CDR designs.
• System integrators: The ability to digitally offset the data sampling clock when using a phase interpolator based CDR allows in-system testing of timing margins in the actual operating environment. Such system-level testing increases the reliability of manufactured systems.
• Consumers: The cost, power, performance, and testability benefits from using phase interpolator based CDRs passes on to products purchased by consumers in the form of lower prices, longer battery life, and better reliability.