Variable Burst Length

Background

Many different types of computing systems use DRAMs. When different types of computing systems can use the same DRAM, they benefit from economies of scale that result from amortized design and manufacturing costs. Although systems in different computing segments may have similar needs for their DRAM capabilities, each computing segment has some unique needs. One such need is burst length, which is the amount of data transferred during memory Read and Write transactions. Some computing segments use memory system architectures that need shorter burst lengths, while others need longer burst lengths. An innovation targeted at satisfying a variety of users makes burst length variable in the DRAM. Variable burst length allows computing systems to choose which burst length to use based on system needs. In the early 1990s Rambus introduced the first DRAM using variable burst length, allowing system manufacturers to tailor the per-request amount of data transferred to the needs of their systems. By introducing variable burst length, a single DRAM can be designed and manufactured that is appropriate for multiple system architectures, resulting in lower costs and greater system flexibility.

Flash memory is another popular memory technology used in many computing systems. Variable burst length has also been adopted in some Flash memory devices. Variable burst length operates in similar manners in DRAMs and Flash memory devices, providing similar benefits to systems that make use of this feature.

What Is Variable Burst Length?

When a DRAM receives a memory read request, it responds by supplying data across the wires of the memory bus. The size of the data block that is transferred in response to the request is based on the burst length of the DRAM. Figure 1 illustrates the difference between a burst length of 4 and a burst length of 8. As the figure shows, a DRAM with a burst length of 8 (shown in the bottom of Figure 1) returns twice as much data in response to a read request as a DRAM with a burst length of 4.

As Figure 1 demonstrates, variable burst length is useful for allowing the same DRAM to be used in different memory systems that require different amounts of data to be transmitted to and from the DRAMs. Although DRAMs with a burst length of 4 can be used to transfer 8 bits of data per wire by performing two read transactions in succession, this requires twice as much address and control bandwidth to initiate the two requests. In systems with limited address or control bandwidth, it may be impossible to provide enough address/control bandwidth to ensure maximum data throughput (See double bus rate technology information). Variable burst length addresses this issue by reducing the amount of address and control bandwidth necessary to transfer data.

Figures 2 and 3 show how variable burst length can be used in two different memory systems that utilize the same DRAM devices. The computer system in Figure 2 includes a CPU, memory controller, and memory, which in this case is on memory modules. This system may correspond to a small form-factor or low-end PC. In this system, the data portion of the memory bus is 64 bits wide, and the CPU accesses data in 64-byte chunks, which may correspond to the cache line size in an internal cache of the CPU. To optimize efficiency in the system, the memory controller configures the DRAMs to have a burst length of 8 so that a block of 64 bytes of data will be transferred from the memory (8 x 64 bits = 64 bytes) in response to a single request from the memory controller.

Figure 3 depicts an architecture representative of a high-end PC, blade, or server. This memory system has a 128-bit wide data portion of the memory bus. Although there are twice as many data lines as in the memory system of Figure 2, both architectures can use the same CPU with the same data block size requirements, thereby allowing CPU manufacturers to leverage one processor design for multiple markets. In this system, if the burst length is set to 8, then the memory modules would respond to a single request from the memory controller with 128 bytes – more than the CPU needs, wasting memory bandwidth. However, by having the flexibility to set the burst length of the memory devices to 4 (4 x 128 bits = 64 bytes), each memory device outputs half as much data as it would for a burst length of 8. This allows the memory controller to maximize the efficiency of the memory system by getting all of the requested data with a single request and without producing unneeded extra data.

Variable burst length allows the same DRAM devices to be used in multiple system architectures, reducing the number of DRAM devices and module architectures needed. The ability to use the same DRAM devices across many systems reduces manufacturing and inventory costs, benefiting system manufacturers and consumers alike. The flexibility that variable burst length supplies ensures that systems can use burst length values best suited to their needs, thereby reducing control bandwidth and ensuring efficient use of the memory bus.

Who Benefits?

Examples of some of the groups that benefit from variable burst length are:

• Processor designers. Variable burst length allows a single DRAM or Flash memory design to be used in multiple memory system architectures. This enables processor designs to operate in multiple markets, which decreases development costs, manufacturing costs based on economies of scale, and inventory costs.
• System integrators. System integrators who serve multiple markets can qualify and stock a single DRAM or Flash memory type for use in multiple product lines. This reduces inventory control costs.
• Memory manufacturers. By using variable burst length, memory manufacturers can leverage a single DRAM or Flash memory design for use in multiple markets, providing similar cost advantages (reduced development, manufacturing, and inventory costs) as those available to processor designers.