R+™ DDR3 Memory Controller Interface
A part of the Rambus R+ solution set, the R+ DDR3 memory interface controller is a highperformance, low-cost solution that allows customers to differentiate their products while improving their time-to-market. R+ DDR3 is fully compatible with industry standards and offers lower risk with improved performance. The R+ DDR3 memory interface can be implemented in a low-cost wire bond package and is capable of supporting data rates of up to 1866 megatransfers per second (MT/s).
- Data rates 1600 to 1866Mbps
- Over 7.4GB/s bandwidth per device
- Multi-modal support for DDR2 and DDR3
- JEDEC compliant
- Silicon proven design
- Supports wire bond or flip-chip packaging
- Includes LabStation™ software environment for bring-up, characterization, and validation in end-user application
The R+ DDR3 incorporates patented innovations such as on-chip Phase-Locked Loops (PLLs), Delay-Locked Loops (DLLs), FlexPhase™ Timing Adjustment circuits, Output Driver Calibration, and On Die Termination (ODT) Calibration to provide a complete memory solution. The PHY also provides backwards compatibility for DDR2 SDRAM applications.
The R+ DDR3 PHY consists of a Command/Address (C/A) macro cell and a variable number of 8-bit Data macro cells. The technology contains all of the necessary components for robust operation including IO pads, PLL, Power Mode Management (PMM), transmit and receive paths, clock distribution, control logic, power distribution and electrostatic discharge (ESD) protection circuitry.
Rambus FlexPhase technology is included in the R+ DDR3 to provide optimum memory system timing, including write-leveling and read-leveling delay adjustment for fly-by topologies. Support is provided for the standard R+ DDR3 write-leveling calibration process performed by the memory controller.
Rambus offers its DDR3 PHY in a PHY development package (PDP) which allows memory interface designers to customize their DDR3 implementation to meet their specific application needs. Through the PDP, Rambus provides all the necessary building blocks including the PHY architecture, schematics, models, generic layout, floor plan, verification IP, implementation documentation, testing documentation, design scripts and simulation files to ensure interface design success.