XDR™2 Innovations

The Rambus XDR™2 memory architecture is the first to incorporate innovations from Rambus' Terabyte Bandwidth Initiative and builds on enhanced versions of key technologies already implemented in the award-winning XDR architecture. New technologies implemented for the first time in XDR 2 memory include 32X Data Rate, Fully Differential Memory Architecture (FDMA), Enhanced FlexPhase™, Flexlink™ C/A, and Micro-threading.

• 32X Data Rate technology transfers 32-bits of data per I/O on every clock cycle. This enables extremely high bit-transfer rates and per device bandwidth while maintaining relatively low system clock speeds. This technology allows the XDR 2 memory system to run at data rates as high as 20Gbps at relatively low and economical system clock speeds.
  
  
• Fully Differential Memory Architecture (FDMA) is the industry’s first implementation of a memory architecture that incorporates differential signaling on all the key signal connections between the memory controller and the XDR 2 DRAM. FDMA enables higher data rates, lower power, and improved signal integrity.
  
  
• Enhanced FlexPhase™ technology enables flexible phase relationships on data and command/address signals, allowing precise on-chip alignment of data with clock. Enhanced FlexPhase improves the sensitivity and capability of FlexPhase for very high performance memory systems operating at data rates of over 6.4Gbps.
  
  
• Flexlink™ C/A is the industry's first full-speed, scalable, point-to-point command/address channel technology. Each FlexLink C/A link provides the command and address information to a DRAM using as few as a single, differential high-speed communications channel. This reduces pin count and area while enabling scalable capacity and flexible access granularity.
  
  
• Micro-threading is a technology that improves access efficiency for advanced applications. Micro-threading increases the useable bandwidth by logically partitioning a traditional 8-bank DRAM core into 16 independently addressable banks. Independent access to what are effectively 16 banks reduces both row and column access granularity and results in a significant performance increase for graphics and multi-core computing workloads.