An exponential rise in data volume, and the meteoric rise of advanced workloads like AI/ML training, requires constant innovation in all aspects of computing. Memory bandwidth is a critical enabler of unleashing the power of processors and accelerators, and the High Bandwidth Memory (HBM) standard has evolved rapidly to deliver the performance required by the most demanding applications.
For current generation HBM2E, Rambus introduced the industry’s fastest memory subsystem capable of 4 gigabits per second (Gbps) operation. With a 1024-bit wide interface, 4 Gbps signaling delivers 512 gigabytes per second (GB/s) of bandwidth. In accelerator architectures with 4-6 HBM2E DRAM devices (each device being a 3D stack of DRAM chips), there’s the capability for 2-3 Terabytes per second (TB/s) of memory bandwidth. That’s enormous, but the appetite for bandwidth is insatiable, so the wheel of innovation needs to keep spinning.
And that brings us to HBM3. The next generation of the HBM standard will increase the supported DRAM chip capacity, increase the supported height of the 3D stack, and of course, increase the data rate for higher bandwidth. In preparation for the coming HBM3 standard, Rambus has announced our HBM3-Ready Memory Subsystem consisting of an integrated PHY and HBM3 memory controller. This HBM3-Ready solution can operate at up 8.4 Gbps, more than doubling the bandwidth of the record-setting Rambus HBM2E Memory Subsystem.
In a next-generation HBM3-based accelerator architecture with 8 HBM3 devices, memory bandwidth jumps to 8.6 TB/s using 8.4 Gbps signaling. While it will take time for the HBM3 DRAM devices to scale to that data rate, designers can immediately benefit from the headroom the Rambus HBM3-Ready Memory Subsystem provides to ensure they can meet their performance targets.
Because, in addition to being the performance leader, Rambus is the HBM market leader as well. With over 50 HBM2/2E implementations, and a first-time right track record second to none, Rambus helps customers speed their products to market. Our complete memory subsystem consisting of PHY and memory controller greatly simplifies design integration. And we provide both interposer and package reference designs to help customers successfully implement HBM’s 2.5D architectures.