Rambus is at DesignCon 2017

This entry was posted on Wednesday, January 25th, 2017.

The DesignCon 2017 expo kicks off on February 2nd in Santa Clara. We’re at booth #833, showcasing our comprehensive suite of Ethernet, PCIe and DDRn IP solutions to solve today’s most challenging data center and networking needs. Rambus technical experts, executives and partners will also be holding a series of talks and technical training sessions listed below.

Rambus at DesignCon

Rambus Technical Session Details

Title: Power Delivery Network Design and Optimization for High-Speed Systems with Si Interposer

Date: Wednesday, February 1, 2017

Time: 9:00 am – 9:45 am

Location: Ballroom C

Speaker: Wendem Beyene, Technical Director, Rambus

As the power supply lowers, designers need to pay closer attention to local bypass capacitor selections to suppress power supply noise and jitter. Although on-chip decaps are used to suppress high-frequency noises, off-chip decaps are often needed to reduce low and mid-frequency noise. The impact of on-package and on-interposer decaps to suppress the mid-frequency noise depends on the design rules of the top layer of the Si interposer. The resistive and capacitive characteristics of Si interposer can determine the effectiveness of the decaps placed on the Si interposer. Thus, careful analysis of interposer and package decaps are required.

Title: Methodology for Reusing the Verification Tests and Efforts Beyond Pre-Silicon Verification

Date: Thursday, February 2, 2017

Time: 3:00 pm – 3:45 pm

Location: Ballroom A

Speakers: Dinesh Malviya, Sr. Manager Engineering, Rambus; Sujith Hiremath, Senior Member of Technical Staff – Verification, Rambus

Functional verification language and methodology has matured and converged to a standard (SystemVerilog and UVM). This trend has improved verification quality and reuse to a significant extent. However, there are many areas where verification reuse is not extended due to environment compatibility. Below are several areas where verification efforts could be leveraged to increase overall efficiency and productivity.

  • Post silicon validation test vectors
  • Firmware code generation
  • DFT macro tests documentation
  • Direct reuse in different verification environments

This paper introduces a new verification methodology for converting SystemVerilog test sequences in to language neutral test sequence. This language neutral test sequence is automatically converted to other language and format for addressing above reuses.

Rambus Training Sessions

Title: An 8b ADC for a 56Gbps PAM4 Receiver

Date: Wednesday, February 1, 2017

Time: 9:20 am – 10:00 am

Location: Great America 3

Speakers: Kenneth C. Dyer, Senior Principal Engineer Architect, Rambus; Shankar Tangirala, Principal Design Engineer, Rambus

The industry move to 56 Gbps PAM4 signaling requires a major update to the SerDes IP architecture. At the heart of these new long reach (35+ dB) designs is an analog to digital converter. In this talk, you will learn about the architectural tradeoffs and design considerations that lead to an optimal ADC configuration. The ADC described consists of 32 X 8 bit SAR channels, a sampling network, and mixed-signal calibration system running at 28 GS/s.

Title: ADC-Based Link Architecture for Multilevel Signaling at 56G

Date: Wednesday, February 1, 2017

Time: 10:15 am – 10:55 am

Location: Great America 3

Speakers: Masum Hossain, Senior Principal Engineer, Rambus; Nhat Nguyen, Sr. Director of Engineering, Architecture & Design, Rambus

The talk will start with the motivation, advantages and challenges of ADC-based SerDes IP design for 56 Gbps PAM4 signaling at over 35 dB. While the ADC enables scalable digital equalization, modeling the ADC non-idealities is also critical to capture link performance. This talk will walk through the modeling techniques of key blocks for the ADC-based link and will conclude with architectural choices and performance of ADC based links running at 56 Gbps over 35+ dB channels.
Title: PCI Express PHY and controller integration at Gen4: PLDA’s proven methodology for first-time silicon success

Date: Wednesday, February 1, 2017

Time: 11:05 am – 11:45 am

Location: Great America 3

Speaker: Trupti Gowda, Field Application Engineer, PLDA Inc.

PLDA is an industry leader in PCIe with 20 years of experience providing IP cores. With the introduction of PCIe GEN4, the protocol has become more complex. PLDA provides fully integrated PCIe Controller and PHY solutions using a proven methodology based on its vast experience integrating its controller with 3rd-party PHY, including Rambus SerDes PHYs, to help the customer with silicon success. In this talk we present details on our methodology for Controller and PHY integration and highlight its benefits to the customers.

Title: Design and Modelling of 2.5D HBM2 Interposer System

Date: Wednesday, February 1, 2017

Time: 2:00 pm – 2:40 pm

Location: Great America 3

Speaker: Yuri Tretiakov, Principal Engineer, Systems / IC Package Design, Rambus
The HBM2 DRAM interface requires both silicon interposer and a package. Interposer design rules and signal routing floorplan need to be carefully chosen using EM simulations and channel analysis. Lossy silicon substrate and slotted ground effects need to be taken into account. In addition, package design needs to be carefully done, especially from minimizing inductance for most critical power supplies point of view. Also, for most critical power supplies on-package decaps need to be properly selected and placed on a package. This talk addresses how these HBM interposer and package design challenges are met for a HBM2 system operating at 2.0Gbps.

Title: SI and PI Challenges of a 2.5D HBM2 Interposer System

Date: Wednesday, February 1, 2017

Time: 2:50 pm – 3:30 pm

Location: Great America 3

Speakers: Ravi Kollipara, Technical Director, Engineering, Rambus; Joohee Kim, Senior Member of Technical Staff II, Rambus

The HBM2 DRAM interface operates at a max data rate of 2.0 Gbps. The silicon interposer channel is highly resistive and hence, RC limited. The HBM2 interface has more than 1600 switching signals which draw power through the TSVs of the silicon interposer and the vias of the BGA package. Hence, the potential exists for significant SSN which can result in eye closure. In addition, the HBM2 DRAM input mask is more stringent than that of the DDR4 DRAM. This talk addresses how these SI and PI challenges are met for a HBM2 system designed to operate at 2.0 Gbps.

Title: HBM2 Controller and PHY Integration

Date: Wednesday, February 1, 2017

Time: 3:45 pm – 4:25 pm

Location: Great America 3

Speaker: Brian Daellenbach, President, Northwest Logic.

The HBM2 DRAM interface operates at a max data rate of 2.0 Gbps. The silicon interposer channel is highly resistive and hence, RC limited. The HBM2 interface has more than 1600 switching signals which draw power through the TSVs of the silicon interposer and the vias of the BGA package. Hence, the potential exists for significant SSN which can result in eye closure. In addition, the HBM2 DRAM input mask is more stringent than that of the DDR4 DRAM. This talk addresses how these SI and PI challenges are met for a HBM2 system designed to operate at 2.0 Gbps.