The PCI Express® (PCIe) interface is the critical backbone that moves data at high bandwidth between various compute nodes such as CPUs, GPUs, FPGAs, and workload-specific accelerators. The rise of cloud-based computing and hyperscale data centers, along with high-bandwidth applications like artificial intelligence (AI) and machine learning (ML), require the new level of performance of PCI Express 5.0.
SerDes PHYs
Analysis, Modeling and Characterization of Multi-Protocol High-Speed Serial Links
Improved analysis, modeling, characterization and correlation methods of multi-protocol high-speed transceivers that utilize T-coil to enhance the transmitter and receiver bandwidth, transmitter FIR filters and receiver CTLE and DFE equalizers is presented. The key circuit blocks are measured and modeled using IBIS-AMI models and the overall system performance including the eye diagrams, BER curves are well correlated to on-die measurements. The paper discuss the procedure taken to model, measure, and verify the high-speed transceivers meet the standard specifications such as return loss, jitter tolerance, BER and convergence of the adaptation equalizers and CDR to optimize the margins for various channels.