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Rambus China Seminar Series: Designing Interfaces for Hyperscale [Shanghai]
May 14, 2019 @ 8:30 am - 4:15 pm
Join us for our seminar series in Shanghai, where we will be discussing the evolving computing landscape, choosing the right solutions for memory and architectures to address the needs of high-performance and hyperscale computing, best practices for memory interface design implementation, SerDes solutions for high-performance and hyperscale computing, and next generation wireline communication interfaces.
Full agenda below. Register here: https://cicmag.com/bbx/2616762-2616762.html
9:45 AM – 10:45 AM – Session 1
The Evolving Computing Landscape: How Modern Applications Are Changing the Way We Process Information
Leading-edge applications like Artificial Intelligence (AI), High-Performance Computing (HPC), and the Internet of Things (IoT) generate enormous amounts of digital data placing tremendous performance, bandwidth, and capacity demands on processors, memory systems and networks. Complicating matters, two of the industry’s traditionally best tools, Moore’s Law and Dennard scaling, can no longer be counted on as the means to improve performance. A new golden age of computer architecture is upon us, as the industry focuses on specialized silicon and new computer and system architectures to meet the demands for higher performance. This presentation will discuss how leading-edge applications are driving change in servers and networks, hyperscale data centers, and mobile/edge/data center computing, and the crucial role well-designed memory systems and high-speed serial interfaces play in achieving future performance and power-efficiency needs.
Speaker: Dr. Steven Woo, Rambus Fellow and Distinguished Inventor, Rambus
10:45 AM – 11:45 AM – Session 2
High-Performance Memory Interfaces: Choosing the Right Solution for Your SoC Design
Leading-edge, high-performance computation power required by cloud applications is limited by memory speed, access throughput and latency. There are a number of memory options and architectures available to address the needs of high-performance (HPC) and hyperscale computing. Each has advantages and tradeoffs that designers and system architects should consider. This presentation will discuss the memory options, their characteristics and suitability for leading-edge applications.
Speakers: Frank Ferro, Senior Director, Product Management, IP Cores, Rambus and Brian Daellenbach, President, Northwest Logic
12:45 PM – 1:45 PM – Session 3
Best Practices for Memory Interface Design Implementation
There are a great many design and implementation considerations for successfully integrating the latest memory solutions into high-performance ASICs and SoCs. A system-level approach covering issues such as package design, thermal analysis, channel modeling and board-level design is crucial to a successful implementation. This presentation will cover best practices for implementing memory interfaces based on Rambus’ many decades of experience designing and implementing memory architectures for the most demanding applications.
Speaker: Arun Vaidyanath, VP Engineering, IP Cores Development, IP Cores, Rambus
1:45 PM – 2:45 PM – Session 4
SerDes Solutions for High-Performance and Hyperscale Computing
AI, machine learning, big data, analytics, and a host of new cloud-based workloads are driving continued evolution in both HPC and hyperscale computing. Application-specific architectures have arisen to optimize performance to the unique requirements of the computational task. Critical to the success of these computing architectures are high-speed SerDes interfaces providing high-bandwidth communications between ASICs and SoCs. This presentation will cover the SerDes solutions that are helping take HPC and hyperscale computing to new levels of performance.
Speakers: Saman Sadr, VP IP Cores Marketing, IP Cores, Rambus and Brian Daellenbach, President, Northwest Logic
3:00 PM – 4:00 PM – Session 5
Next Generation Wireline Communication Interfaces
Given the enormous growth in internet traffic, hyperscale data centers are witnessing a doubling of data rates every two years. As an example of this trend, terabit switches have jumped from 3.2Tbps (2014), to 6.4Tbps (2016), to 12.8Tbps (2018) and are projected to reach 28.6Tbps in 2020. Concurrently, links between servers and network devices are moving to 400GbE to carry these rapidly growing traffic loads. This presentation will cover the networking SerDes solutions critical to the ongoing hyperscale revolution including the latest SerDes solutions for 112G.
Speaker: Saman Sadr, VP IP Cores Marketing, IP Cores, Rambus