Improved analysis, modeling, characterization and correlation methods of multi-protocol high-speed transceivers that utilize T-coil to enhance the transmitter and receiver bandwidth, transmitter FIR filters and receiver CTLE and DFE equalizers is presented. The key circuit blocks are measured and modeled using IBIS-AMI models and the overall system performance including the eye diagrams, BER curves are well correlated to on-die measurements. The paper discuss the procedure taken to model, measure, and verify the high-speed transceivers meet the standard specifications such as return loss, jitter tolerance, BER and convergence of the adaptation equalizers and CDR to optimize the margins for various channels.
Memory + Interfaces
The demands on server performance continue to increase at a tremendous pace. New requirements from large in-memory databases that are powering today’s cloud services and advanced analytics tools are arriving just as the impact of Moore’s Law is starting to slow. This is setting up a classic performance challenge that requires rethinking some of the core elements of today’s server architectures, particularly when it comes to memory. One key new opportunity is for high-speed server memory interface chipsets, which enable high-speed memory performance without compromising on memory capacities. Companies looking to optimize their server memory architecture designs, and improve their overall server performance and reliability, should give serious consideration to optimized DDR4 memory interface chipsets, which enhance the performance of server memory modules.
The Rambus 6 Gbps Multi-Protocol SerDes (MPS) PHYs are a general-purpose, high-speed serial link subsystem that support data rates from 1.25 Gbps to 6.375 Gbps. Optimized for power and area, they can compete even with single-protocol solutions.
The Rambus 12 Gbps Multi-Protocol SerDes (MPS) PHYs are a general-purpose, high-speed serial link transceiver subsystem that support data rates from 1.25 Gbps to 12 Gbps. Optimized for power and area in high-loss channels, our 12G MPS PHYs are suitable for a broad range of enterprise-class systems.
The Rambus 16 Gbps Multi-Protocol SerDes (MPS) PHYs are a high-performance serial link subsystem. Optimized for power and area in challenging, high-loss channels typical of copper backplanes and long runs of cable, our 16G MPS PHYs are ideal for networking, telecom and data center systems.
Our On-Chip Power Supply Noise Monitor has been developed to overcome the characterization challenges of low-power, high-performance interfaces and electronic systems. It is a compact IP block embedded on-chip and works in conjunction with our LabStation™ Validation Platform to enable noise measurements directly on the chip.