The Northwest Logic Expresso 5.0 controller core is designed for maximum performance and ease of use for PCI Express (PCIe) 5.0 applications. It comprises a complete SerDes subsystem with the Rambus PCIe 5.0 PHY or can integrate with PIPE 5.2-compliant 3rd-party PHYs. The Expresso 5.0 controller supports PCIe 5.0, 4.0, 3.0 and 2.0.
Memory + Interfaces
The Rambus PCI Express (PCIe) 5.0 and Compute Express Link (CXL) PHY is a low-power, area-optimized, silicon IP core designed with a system-oriented approach to maximize flexibility and ease of integration. It comprises a complete SerDes subsystem with the Northwest Logic Expresso 5.0 controller core or can integrate with PIPE 5.2-compliant 3rd-party controllers. The PCIe 5.0 PHY supports PCIe 5.0, 4.0, 3.0 and 2.0 and has full support for manufacturability.
This IDC Technology Spotlight Report, sponsored by Rambus, highlights key, often hidden, memory and interface technologies that are enabling high performance electronic systems to serve the disruptive trends of the next decade like IoT, 5G, and Artificial Intelligence.
The virtuous cycle of increased computing power enabling new applications which demand more computing power continues unabated. Today, applications spanning AI, autonomous vehicles, video streaming, AR and VR all demand more bandwidth, lower latencies and higher speeds. In response, the SoCs powering the terabit routers and switches at the heart of the network must run even faster. The upgrade to 112G SerDes represents the latest advancement in high-speed signaling technology enabling communication within and between network devices.
The Rambus 112G LR MPS PHY is a comprehensive IP solution designed to provide reliable performance across challenging long-reach signaling environments for next-generation networks and hyper-scale data centers. It supports PAM-4 and NRZ signaling and data rates from 10.31 to 106.25 Gbps across copper and backplane channels with more than 35dB insertion loss. At the heart of the 112G MPS architecture is an ADC operating at 56 GS/s that allows for adjustable power and improved performance while providing low BER.
With GDDR PHYs providing a maximum bandwidth of up to 64 GB/s, it is critical for ASIC designers to ensure that devices and systems aren’t affected by signal integrity issues. This is precisely why the Rambus GDDR6 PHY engineering team makes extensive use of modeling and simulation tools, as well as providing highly-programmable circuits, debug interfaces and utilities. Moreover, our engineering team comprises a range of in-house experts that participate in all stages of the GDDR6 PHY design which is available on leading FinFET process nodes. These include package and PCB design experts and layout gurus, as well as signal integrity and power integrity specialists. On the engineering side, the Rambus GDDR6 PHY leverages our system-aware design methodology to facilitate flexible product integration. Specifically, we provide full system signal and power integrity analysis to optimize performance and chip layout.