Memory PHYs

>Memory PHYs

Beyond pixels and shaders: Non-graphical uses for GDDR6

Graphics Double Data Rate (GDDR) memory is a type of synchronous graphics random-access memory (SGRAM) with a high-speed interface. First available in 2007, the previous generation of GDDR, GDDR5, has evolved well beyond its expected [...]

Taking a closer look at the Rambus GDDR6 PHY IP Core

Once targeted exclusively at GPUs, GDDR use cases are rapidly expanding beyond traditional GPU and graphic applications. This is primarily due to the demand for increased bandwidth across a diverse set of market verticals – [...]

Understanding the post Moore-Era data center

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Steven Woo, the vice president of systems and solutions and distinguished inventor in Rambus’ Office of the CTO, recently authored an article for Semiconductor Engineering that explores the data center in 2018 and beyond. As [...]

Going beyond GPUs with GDDR6

The origins of GDDR The origins of modern graphics double data rate (GDDR) memory can be traced back to GDDR3 SDRAM. Designed by ATI Technologies, GDDR3 made its first appearance in nVidia's GeForce FX 5700 [...]

Introducing the Rambus GDDR6 Memory PHY

The Rambus GDDR6 Memory PHY IP Core Rambus has officially announced its GDDR6 (Graphics Double Data Rate) Memory PHY IP Core. According to Luc Seraphin, SVP and general manager of the Rambus Memory and Interfaces [...]

Let’s talk about 7nm

Frank Ferro, a senior director of product management at Rambus, recently penned an article for Semiconductor Engineering about the promises and challenges of 7 nanometers (nm). According to Ferro, the demand for 7nm is driving [...]

Pre-verified chiplets gain traction as NRE costs rise


Pre-verified chiplets Ann Steffora Mutschler of Semiconductor Engineering recently penned an article that explores how the concept of building silicon from pre-verified chiplets is beginning to gain traction – as the semiconductor industry seeks to [...]

Rambus validates interoperability of DDR4 high-performance memory IP solution for Arm-based data center systems

Rambus’ DDR4 PHY and Arm’s CoreLink DMC-620 Dynamic Memory Controller Today, we announced the validated interoperability of Rambus’ DDR4 PHY and Arm’s CoreLink DMC-620 Dynamic Memory Controller. Together, these IP blocks offer speeds of up [...]

Living on the edge with 5G and fog computing

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From 4G to 5G The current 4G cellular networks that drive our computers, tablets and smartphones are poised for a major upgrade as we approach 5G. To understand where we’re going with 5G, we need [...]

Rambus highlights HBM2 PHY collaboration at GLOBALFOUNDRIES Technology Conference


HBM2 PHY We are showcasing our HBM2 PHY at the GLOBALFOUNDRIES Technology Conference at the Hyatt Regency Santa Clara (table #6). Designed for systems that require low latency and high bandwidth memory, our HBM2 PHY [...]

5G connections to hit 1.4 billion by 2025

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Juniper Research analysts are forecasting 1.4 billion 5G connections by 2025, an increase from  just 1 million – upon commercial launch of 5th generation wireless systems – in 2019. Unsurprisingly, the U.S. alone is expected [...]

Rambus and Northwest Logic certify HBM2 interoperability

Rambus has validated interoperability between its HBM2 PHY and Northwest Logics’ HBM2 Memory Controller Core. The combined HBM2 solution is designed to support high-performance networking and server applications in the data center and communications markets [...]

GLOBALFOUNDRIES highlights HBM2 PHY collaboration with Rambus

2Tbps multi-lane HBM2 PHY Earlier this month, GLOBALFOUNDRIES demonstrated silicon functionality of a 2.5D packaging solution for its high-performance 14nm FinFET FX-14 integrated design system for application-specific integrated circuits (ASICs). The 2.5D ASIC solution includes [...]

GLOBALFOUNDRIES demonstrates 2.5D high-bandwidth memory (HBM) solution

GLOBALFOUNDRIES has demonstrated silicon functionality of a 2.5D packaging solution for its high-performance 14nm FinFET FX-14™ integrated design system for application-specific integrated circuits (ASICs). According to Kevin O’Buckley, VP of ASIC product development at GF, [...]

Memory and the IoT

Semiconductor Engineering’s Ed Sperling and Jeff Dorsch recently wrote an article about the challenges of chip design in the age of the IoT. As Sperling notes, this includes sensors, various types of processors, a growing [...]

HBM2 continues to ramp

Samsung ramps volume production of 8GB HBM2 Earlier this month, Samsung confirmed an increase in production volume of its 8-gigabyte (GB) High Bandwidth Memory-2 (HBM2) to meet growing market needs across a wide range of [...]

TIRIAS Research analyzes Rambus’ memory and high-speed interfaces strategy

Jim McGregor, principal analyst at TIRIAS Research, recently spoke with Gary Hilson of the EE Times about Rambus’ 56G SerDes PHY. More specifically, the analog-to-digital converter (ADC) and (DSP) architecture of Rambus’ 56G SerDes PHY [...]

Keeping up with Ethernet

Gary Hilson of the EE Times has written a detailed article about Rambus’ 56G SerDes PHY. As Hilson notes, the analog-to-digital converter (ADC) and (DSP) architecture of Rambus’ 56G SerDes PHY is designed meet the [...]

Why HBM2 is all about the PHY

Rambus’ Bill Fuller recently penned an article for Semiconductor Engineering about HBM2 DRAM. As Fuller observes, HBM DRAM is currently used in graphics, high-performance computing (HPC), server, networking and client applications. Recent examples of second-generation [...]

The rise of high bandwidth memory (HBM)

Semiconductor Engineering’s Ann Steffora Mutschler recently penned an article about high bandwidth memory (HBM). As Mutschler observes, the latest iteration of HBM continues its rise as a viable contender in the memory space. Indeed, HBM [...]

Building a robust HBM2 PHY

What is HBM? HBM is a high-performance memory that features reduced power consumption and a small form factor. More specifically, it combines 2.5D packaging with a wider interface at a lower clock speed (as compared [...]

The Rambus HBM GEN2 PHY: A closer look

Earlier this week, Rambus announced the availability of its new High Bandwidth Memory (HBM) Gen2 PHY. Designed for systems that require low latency and high bandwidth memory, the Rambus HBM PHY, built on the GLOBALFOUNDRIES [...]

Rambus launches High Bandwidth Memory PHY on GLOBALFOUNDRIES 14nm LPP

Rambus has announced the availability of its High Bandwidth Memory (HBM) Gen2 PHY developed for the GLOBALFOUNDRIES FX-14TM ASIC Platform. Designed for systems that require low latency and high bandwidth memory, the Rambus HBM PHY, built [...]

Rambus microsite goes live on The Next Platform

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A new microsite curated by Rambus is now live on The Next Platform. According to Kendra De Berti, Director, Solutions Marketing at Rambus, the microsite hosts a wide range of in-depth content on applications from [...]

Intel says DDR4 is ramping quickly


Last week at IDF 2016, Intel executive Geof Findley presented a comprehensive overview of the memory industry ecosystem. According to Findley, DDR4 is ramping quickly and should hit 31% of shipments during the second quarter [...]

ChipEstimate and Rambus look beyond DDR4


Frank Ferro, a senior director of product management at Rambus, has penned an article for ChipEstimate about the future of DRAM in the age of the IoT. According to Ferro, the semiconductor industry has traditionally relied [...]

EE Times takes a closer look at Rambus’ 14nm R+ DDR4 PHY

Gary Hilson of the EE Times has covered Rambus’ recent announcement about the development of its R+ DDR4 PHY on GLOBALFOUNDRIES 14nm LPP process. As the journalist notes, the silicon is the first production-ready 3200 [...]

R+ DDR4 PHY developed on GLOBALFOUNDRIES 14nm LPP process

Rambus has confirmed the development of its R+ DDR4 PHY on the GLOBALFOUNDRIES 14nm LPP process. “As part of a comprehensive suite of memory and SerDes interface offerings for networking and data center applications, we [...]

Optimizing memory bandwidth

Frank Ferro, a senior director of product management at Rambus, recently sat down with Ed Sperling of Semiconductor Engineering and other industry participants to discuss the slew of new memory initiatives and entrants. According to [...]

Exploring 2.5D packaging and beyond


Frank Ferro, a Senior Director of Product Marketing at Rambus, recently participated in a Semiconductor Engineering roundtable discussion about 2.5D and advanced packaging. According to Ferro, 2.5D can succeed if customer demand overcomes the additional [...]

From consoles to VR


The Atari 2600 (or VCS) – which hit the nascent video game market back in 1977 – packed 128 bytes RAM and an 8-bit MOS 6507 CPU clocked at a mere 1.19 MHz. According to [...]

Architecting new memory for the IoT

The once indefatigable Moore’s Law is beginning to slow, even as data, driven by a burgeoning Internet of Things (IoT), continues to increase exponentially. Consequently, a slew of new memory architectures, including those utilizing 2.5D [...]

ReRAM gains traction in the memory space

Writing for Semiconductor Engineering, Michael Watts reports that Resistive RAM (ReRAM) appears to be gaining traction. “Once considered a universal memory candidate—a replacement for DRAM, flash and SRAM—ReRAM is carving out a niche between DRAM [...]

Rambus is @ ARMTechCon 2015

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Rambus – a silver sponsor of ARM TechCon 2015 – is kicking off the show this morning with a series of live demos centered on the burgeoning Internet of Things (IoT). “The vision of the [...]

When memory and storage converge

Earlier this week, Rambus Chief Scientist Craig Hampel gave a keynote presentation at MemCon 2015 that explored the increasingly blurred lines between memory and storage. As Hampel notes, devices used as memory are typically volatile, [...]

Moore’s Law: From 16 kB to 16GB


James Sanders of TechRepublic has confirmed that 16 GB SO-DIMM modules are now starting to become generally available from multiple vendors. “[This] eases RAM constraints in devices that have a limited number of slots for [...]

Minding the memory gap

Mark LaPedus of Semiconductor Engineering recently reported that memory chips and storage devices are struggling to keep pace with the growing demands of data processing. “To solve the problem, chipmakers have been working on several next-generation [...]

Memory price dip to spur DDR4 adoption

KitGuru’s Anton Shilov reports that DDR4 prices have dropped approximately 25% since late June. “According to DRAMeXchange, the world’s leading computer memory tracker, one 4Gb DDR4 chip rated to run at 2133MHz cost $3.618 on [...]

Building bridges with DRAM vendors


Analysts at IHS Electronics say Rambus’ change in strategy from intellectual property (IP) licensing house to chipmaker has been “well received” by its customers. “Rambus has announced recently that it would begin developing server memory [...]

Understanding the memory-storage pyramid

Loren Shalinsky, a Strategic Development Director at Rambus, recently penned a detailed article for Semiconductor Engineering that explores the memory-storage hierarchy. As he puts it, the hierarchy, or pyramid, is a particularly succinct method of [...]

Navigating the DDR4 adoption road map

The projected adoption rate of DDR4 as the dominant industry memory standard was a major topic of discussion at Intel’s Developer Forum earlier this month, with the company confirming DDR4-2400 support for its upcoming Xeon [...]

TECHnalysis Research talks Rambus server memory chipsets


Bob O’Donnel of TECHnalysis Research recently published a white paper describing the critical role memory server chipsets play in facilitating high-speed DDR4 designs. “With the introduction of DDR4, server system designers can leverage DRAM that runs [...]

Ely Tsern talks memory interface chipsets with The Platform


Ely Tsern, VP and chief technologist for the Rambus Memory and Interfaces division, recently sat down with Nicole Hemsoth of The Platform to discuss the launch of the company’s server memory interface chipset. “Memory today, [...]

Is DRAM adhering to Moore’s Law?

Writing for PC Magazine, Michael J. Miller notes that although most of the discussion around Moore’s Law has thus far focused on logic chips, the memory industry has clearly entered a transitional stage. “DRAM shrinks [...]

Server market growth tied to increased memory demand


Loren Shalinsky, a Strategic Development Director at Rambus, recently penned an article for Semiconductor Engineering that explores how server market growth has prompted a salient increase in memory demand. “A high-end server can have 48 or [...]

PC World packs 128GB of DDR4 – into a single PC

PC World executive editor Gordon Mah Ung recently announced that his team successfully “smashed right through” the traditional 64GB system RAM barrier. “[The] barrier has vexed consumer computing for years now. Mainstream desktop PCs have [...]

Increasing crop yields with Big Data


The Farmers Business Network (FBN) is currently working on an initiative to break down agricultural data on millions of acres of U.S. farmland – while providing real-world results on the performance of various seed and [...]

Report: Intel Skylake Xeons could feature 28 cores, 6 memory channels

ExtremeTech’s Joe Hruska recently analyzed a set of leaked slides that suggest Intel’s plans for its upcoming Xeon cores may “stretch farther into the stratosphere” than originally predicted. “[The] new data purports to show Intel’s [...]

Report: Intel’s Skylake-S is primed for DDR4


Writing for KitGuru, Anton Shilov says Intel’s upcoming Skylake-S architecture will promote DDR4 “considerably more aggressively” than initially believed. “Although [the] integrated memory controller of Skylake supports different types of DRAM, the processors will not [...]

The DDR5-HBM connection


Frank Ferro, senior director of product marketing at Rambus, recently told SemiconductorEngineering’s Ed Sperling that he was looking forward to seeing what the company could do for next-gen DDR5 as well as evolving high-bandwidth memory [...]