Smart Data Acceleration

>Smart Data Acceleration

Health care industry eyes FPGAs for data acceleration

Edico Genome CEO Pieter van Rooyen recently penned an article for XConomy about the reconfigurable future of health care. As van Rooyen points out, the industry must adopt more powerful computing tools than traditional CPU-based [...]

FPGAs take on convolutional neural networks

In the context of machine learning, a convolutional neural network (CNN, or ConvNet) can perhaps best be defined as a category of feed-forward artificial neural network in which the connectivity pattern between its neurons is [...]

Designing new memory tiers for the data center

Electroiq recently posted an article about Linley’s Cloud Hardware Conference. As the publication explains, the explosive growth in demand for bandwidth and cloud computing capacity poses a new set of challenges and opportunities for the semiconductor [...]

FPGAs are shaping the computing platforms of the future

Steven Woo, VP of Systems and Solutions at Rambus, recently penned an article for Semiconductor Engineering about how FPGAs are helping to shape the computing platforms of the future. As Woo notes, Moore’s Law, which [...]

The evolution of embedded FPGAs

Brian Bailey of Semiconductor Engineering observes that systems on chip have been manufactured with numerous processing variants ranging from general-purpose CPUs to DSPs, GPUs and custom processors which are highly optimized for certain tasks. “When none [...]

Looking beyond Dennard Scaling

Robert H. Dennard co-authored his now-famous paper for the IEEE Journal of Solid State Circuits way back in 1974. Essentially, Dennard and his engineering colleagues observed that as transistors are reduced in size, their power [...]

Microsoft catapults FPGAs to new heights

,

Karl Freund of Moore Insights and Strategy recently penned an article for Forbes about Microsoft’s extensive deployment of FPGA’s in the data center and beyond. As Freund notes, Microsoft currently uses field programmable gate arrays [...]

Maximizing Von Neumann architecture

,

In 1945, mathematician and physicist John von Neumann described a design architecture for an electronic digital computer in the First Draft of a Report on the EDVAC. Also known as the Princeton architecture, the design [...]

Rambus inks license agreement with Xilinx

,

Rambus has signed a license agreement with Xilinx that covers Rambus’ patented memory controller, SerDes and security technologies. In addition, the two companies have agreed to evaluate potential collaboration on the use of Rambus’ CryptoManager [...]

Managing memory more efficiently with Milk

Researchers from MIT’s Computer Science and Artificial Intelligence Laboratory (CSAIL) have introduced  a programming language extension known as Milk that allows app developers to manage memory more efficiently in programs with scattered data points in [...]

The role of FPGA acceleration in the data center and beyond

The International Conference on Field-Programmable Logic and Applications recently convened in Lausanne, Switzerland. As Christoforos Kachris, a senior researcher at the National Technical University of Athens notes, exploring the role of FPGAs in the data [...]

Rethinking system architecture as Moore’s Law wanes

,

Ed Sperling of Semiconductor Engineering observes that chipmakers are increasingly relying on architectural and micro-architectural changes as the “best hope” for optimizing power and performance across markets, process nodes and price points. “While discussion about the [...]

Rambus microsite goes live on The Next Platform

, , , ,

A new microsite curated by Rambus is now live on The Next Platform. According to Kendra De Berti, Director, Solutions Marketing at Rambus, the microsite hosts a wide range of in-depth content on applications from [...]

Accelerating high performance computing systems

Esthela Gallardo and Patricia J. Teller have penned an article for HPC Wire that explores the various challenges associated with cross-accelerator performance profiling. As Gallardo and Teller note, high performance computing (HPC) systems are comprised of [...]

Exploring future memory requirements for quantum computing

,

Quantum computing utilizes quantum-mechanical phenomena, including superposition and entanglement, to perform operations on data. According to Wikipedia, quantum computers differ from traditional binary digital electronic systems based on transistors. To be sure, digital computing encodes [...]

Building a seismic supercomputer in the shadow of Dennard Scaling

,

Bert Beals of Cray Inc. recently told the Digital Energy Journal that the industry can no longer simply build an efficient supercomputer for seismic processing by simply adding more processors. Indeed, because Dennard Scaling no [...]

Smart Data Acceleration with FPGAs and DRAM

The proliferation of connected devices has significantly increased the amount of data being captured, moved and analyzed. This trend is expected to continue well into the foreseeable future as the rapidly burgeoning Internet of Things [...]

Rambus eyes the future of smart ticketing

,

Now a part of Rambus’ security division, Ecebs provides smartcard solutions for governments, transport operators, banks and systems integrators. This makes Rambus one of the leading providers of ITSO-compliant smart ticketing solutions. The strategic addition [...]

Understanding Dennard scaling

,

In 1974, Robert H. Dennard co-authored a now-famous paper for the IEEE Journal of Solid State Circuits. Essentially, Dennard and his engineering colleagues observed that as transistors are reduced in size, their power density stays [...]

The growing demand for FPGAs in servers and data centers

Jeff Dorsch of Semiconductor Engineering recently noted that there are a number of distinct advantages and drawbacks to various compute engines available on the market today. “[For example], CPUs offer high capacity at low latency. [...]

Open sourcing Moore’s Law

,

Nicole Hemsoth of The Next Platform recently observed that while Moore’s Law has yet to fully run its course, organizations such as the IEEE, along with individual device makers, are already thinking their way “out [...]

The system bottlenecks of Moore’s Law

Ed Sperling of Semiconductor Engineering recently noted that rightsizing chip architecture has become more complex in recent years. Essentially, rightsizing is a method of targeting chips to specific application needs – ensuring sufficient performance, while [...]

Balancing cores and memory with Smart Data Acceleration

Ed Sperling of Semiconductor Engineering recently noted that adding more cores to a processor doesn’t necessarily improve system performance. In fact, designing the wrong size or type of core may actually waste power. “This has [...]

New monetization opportunities for the IoT

, ,

Steven Woo, VP of Solutions Marketing at Rambus, recently participated in an Internet of Things (IoT) Summit panel discussion about the creation of new monetization opportunities in the burgeoning space. As Woo noted, chip design [...]

Going beyond DRAM with Smart Data Acceleration

Ed Sperling of Semiconductor Engineering recently noted that new memory types and approaches are being developed as Moore’s Law begins to slow. “What fits where in the memory hierarchy is becoming less clear as the [...]

Optimizing memory for next-gen computing

Semiconductor Engineering Editor in Chief Ed Sperling recently noted that getting data in and out of memory is just as important as optimizing the speed and efficiency of a processor. “[Nevertheless], for years design teams [...]

Eliminating system bottlenecks with smart data acceleration

To many in the industry, system memory is viewed as little more than a silicon holding pen for temporarily storing program commands and data during execution. Nevertheless, the dramatic growth of Big Data – driven [...]

A closer look at Rambus’ SDA research platform

Rambus’ Smart Data Acceleration (SDA) research platform focuses on architectures designed to offload computing closer to very large data sets at multiple points in the memory and storage hierarchy. Potential use case scenarios include real-time [...]

Rambus partners with Los Alamos National Laboratory on smart data acceleration

The Los Alamos National Laboratory (LANL) is currently evaluating various aspects of Rambus’ Smart Data Acceleration (SDA) Research Program. Deployed at LANL, the SDA platform is designed to optimize the performance of in-memory databases, graph [...]

A modular approach to Big Data

Driven by Big Data and new applications, modern servers and data centers are out of synch with current demands – due to increasing requirements for real-time access to large amounts of information. That is precisely [...]

Data centers need a new paradigm

Semiconductor Engineering editor in chief Ed Sperling has written an article exploring the evolution of the data center in the context of the Cloud. As Sperling notes, corporate data centers are notorious for their reluctant adoption [...]

A modular homeostasis for next-gen data centers

,

Writing for ITBusinessEdge, Arthur Cole confirms that modular infrastructure has gained a firm footing in the data center industry. To be sure, nearly all of the platforms currently on the market are optimized for scale-out, [...]