Designing automotive memory

Semiconductor Engineering’s Ann Steffora Mutschler recently penned an article about memory design. As Mutschler notes, memory design considerations are impacted by a range of factors, including cost, power, bandwidth and latency. “When it comes to [...]

The future of NRZ and PAM4

Earlier this month, EDN’s Martin Rowe wrote an article that explores various industry viewpoints – shared at a DesignCon 2018 panel – about the future of NRZ (non-return-to-zero). According to Rowe, four-level pulse amplitude modulation (PAM4) [...]

Why Mobile World Congress is the new Consumer Electronics Show

Mobile World Congress (MWC), originally known as the GSM World Congress when it held its inaugural event in Cannes back in 1987, is the preeminent “everything mobile” conference featuring prominent mobile operators, device manufacturers, technology [...]

Taking a closer look at the Rambus GDDR6 PHY IP Core

Once targeted exclusively at GPUs, GDDR use cases are rapidly expanding beyond traditional GPU and graphic applications. This is primarily due to the demand for increased bandwidth across a diverse set of market verticals – [...]

Rambus highlights HBM2 PHY collaboration at GLOBALFOUNDRIES Technology Conference


HBM2 PHY We are showcasing our HBM2 PHY at the GLOBALFOUNDRIES Technology Conference at the Hyatt Regency Santa Clara (table #6). Designed for systems that require low latency and high bandwidth memory, our HBM2 PHY [...]

Rambus and Northwest Logic certify HBM2 interoperability

Rambus has validated interoperability between its HBM2 PHY and Northwest Logics’ HBM2 Memory Controller Core. The combined HBM2 solution is designed to support high-performance networking and server applications in the data center and communications markets [...]

Memory buffer chips: The Amdahl-Moore’s Law connection

John Eble, a senior director of technical product marketing at Rambus, recently penned an article for Semiconductor Engineering about memory buffer chips. As Eble notes, Moore’s Law, which observes that available transistors in an integrated [...]

Understanding the role of buffer chips in the evolving data center

Rambus VP of Systems and Solutions Steven Woo recently penned an article for ChipEstimate about the changing data center. According to Woo, the evolution of computing from the PC-centric world of the 1980's-1990's to today's [...]

The rise of high bandwidth memory (HBM)

Semiconductor Engineering’s Ann Steffora Mutschler recently penned an article about high bandwidth memory (HBM). As Mutschler observes, the latest iteration of HBM continues its rise as a viable contender in the memory space. Indeed, HBM [...]

Designing new memory tiers for the data center

Electroiq recently posted an article about Linley’s Cloud Hardware Conference. As the publication explains, the explosive growth in demand for bandwidth and cloud computing capacity poses a new set of challenges and opportunities for the semiconductor [...]

Optimizing data centers with DDR4 buffer chips

DDR4 memory delivers up to 1.5x performance improvement over DDR3, running at 2.4Gbps- 3.2 Gbps, while reducing power by 25% on the memory interface. However, the shift to higher speeds degrades electrical signal integrity, especially [...]

Intel says DDR4 is ramping quickly


Last week at IDF 2016, Intel executive Geof Findley presented a comprehensive overview of the memory industry ecosystem. According to Findley, DDR4 is ramping quickly and should hit 31% of shipments during the second quarter [...]

ChipEstimate and Rambus look beyond DDR4


Frank Ferro, a senior director of product management at Rambus, has penned an article for ChipEstimate about the future of DRAM in the age of the IoT. According to Ferro, the semiconductor industry has traditionally relied [...]

EE Times takes a closer look at Rambus’ 14nm R+ DDR4 PHY

Gary Hilson of the EE Times has covered Rambus’ recent announcement about the development of its R+ DDR4 PHY on GLOBALFOUNDRIES 14nm LPP process. As the journalist notes, the silicon is the first production-ready 3200 [...]

A look back at the Nintendo 64 (N64)

The long-awaited Nintendo 64 hit the hot neon city streets of Japan back in June 1996. Powered by a 64-bit NEC VR4300 CPU clocked at 93.75 MHz, the fifth generation console was one of the [...]

Optimizing memory bandwidth

Frank Ferro, a senior director of product management at Rambus, recently sat down with Ed Sperling of Semiconductor Engineering and other industry participants to discuss the slew of new memory initiatives and entrants. According to [...]

Exploring 2.5D packaging and beyond


Frank Ferro, a Senior Director of Product Marketing at Rambus, recently participated in a Semiconductor Engineering roundtable discussion about 2.5D and advanced packaging. According to Ferro, 2.5D can succeed if customer demand overcomes the additional [...]

From consoles to VR


The Atari 2600 (or VCS) – which hit the nascent video game market back in 1977 – packed 128 bytes RAM and an 8-bit MOS 6507 CPU clocked at a mere 1.19 MHz. According to [...]

Waging 21st century cyber-warfare

Cyber-warfare is emerging as the most sophisticated battleground of the 21st century. “In fact, the military in all major countries make it a priority,” Ernest Worthman of Semiconductor Engineering recently observed. “Collectively they are spending tens of [...]

Optimizing memory for next-gen computing

Semiconductor Engineering Editor in Chief Ed Sperling recently noted that getting data in and out of memory is just as important as optimizing the speed and efficiency of a processor. “[Nevertheless], for years design teams [...]

When memory and storage converge

Earlier this week, Rambus Chief Scientist Craig Hampel gave a keynote presentation at MemCon 2015 that explored the increasingly blurred lines between memory and storage. As Hampel notes, devices used as memory are typically volatile, [...]

The importance of understanding bandwidth

Did you know that the terms “latency” and “bandwidth” are frequently misused? According to Loren Shalinsky, a Strategic Development Director at Rambus, latency refers to how long the CPU needs to wait before the first [...]

A modular approach to Big Data

Driven by Big Data and new applications, modern servers and data centers are out of synch with current demands – due to increasing requirements for real-time access to large amounts of information. That is precisely [...]

Understanding the memory-storage pyramid

Loren Shalinsky, a Strategic Development Director at Rambus, recently penned a detailed article for Semiconductor Engineering that explores the memory-storage hierarchy. As he puts it, the hierarchy, or pyramid, is a particularly succinct method of [...]

Google wants 5 petabit switching

The Platform’s Timothy Prickett Morgan reports that Google is eyeing networking throughput capabilities of 5 petabits per second. However, as Google Fellow Amin Vahdat recently pointed out, the industry currently “underprovisions” networks because it doesn’t [...]

Data centers need a new paradigm

Semiconductor Engineering editor in chief Ed Sperling has written an article exploring the evolution of the data center in the context of the Cloud. As Sperling notes, corporate data centers are notorious for their reluctant adoption [...]

Report: Intel Skylake Xeons could feature 28 cores, 6 memory channels

ExtremeTech’s Joe Hruska recently analyzed a set of leaked slides that suggest Intel’s plans for its upcoming Xeon cores may “stretch farther into the stratosphere” than originally predicted. “[The] new data purports to show Intel’s [...]

The DDR5-HBM connection


Frank Ferro, senior director of product marketing at Rambus, recently told SemiconductorEngineering’s Ed Sperling that he was looking forward to seeing what the company could do for next-gen DDR5 as well as evolving high-bandwidth memory [...]

PayPal deploys ARM-based X-Gene servers

Applied Micro CEO and president Paramesh Gopi recently confirmed that PayPal has “deployed and validated” the ARM-powered X-Gene server-on-a-chip. According to Gopi, Paypal represents one of the many hyperscale data center customers the company is [...]

Xiaomi’s Mi Note Pro is loaded with 4GB of RAM

Announced earlier this month at CES 2015, the Asus Zenfone 2 features a 64-bit Intel Atom Z3580 processor and supports up to 4GB LPDDR3 DRAM. As we previously confirmed on Rambus Press, the Zenfone 2 [...]

Building power conscious data centers

Writing for EnterpriseTech, George Leopold notes that data center energy consumption will only continue to increase in the near future – even as regulators attempt to rein in carbon emissions at coal-fired plants tasked with [...]

A modular homeostasis for next-gen data centers


Writing for ITBusinessEdge, Arthur Cole confirms that modular infrastructure has gained a firm footing in the data center industry. To be sure, nearly all of the platforms currently on the market are optimized for scale-out, [...]