Frank Ferro

>Frank Ferro

Understanding HBM design challenges

HBM2 @ 256GB/s As Semiconductor Engineering’s Ann Steffora Mutschler observes, high-bandwidth memory (HBM) enables lower power consumption per I/O, as well as higher bandwidth memory access with a more condensed form factor. This is accomplished [...]

Designing automotive memory

Semiconductor Engineering’s Ann Steffora Mutschler recently penned an article about memory design. As Mutschler notes, memory design considerations are impacted by a range of factors, including cost, power, bandwidth and latency. “When it comes to [...]

Let’s talk about 7nm

Frank Ferro, a senior director of product management at Rambus, recently penned an article for Semiconductor Engineering about the promises and challenges of 7 nanometers (nm). According to Ferro, the demand for 7nm is driving [...]

Understanding peak power limitations in the data center

Semiconductor Engineering’s Anna Steffora Mutschler has written an article about how peak power poses a serious design challenge for chips, electronic systems and data centers. Issues related to peak power, says Mutschler, have become more [...]

Rambus highlights HBM2 PHY collaboration at GLOBALFOUNDRIES Technology Conference


HBM2 PHY We are showcasing our HBM2 PHY at the GLOBALFOUNDRIES Technology Conference at the Hyatt Regency Santa Clara (table #6). Designed for systems that require low latency and high bandwidth memory, our HBM2 PHY [...]

The challenges of IP reuse

Semiconductor Engineering’s Ed Sperling recently penned an article about the challenges of IP reuse. The basic business proposition for third-party IP, says Sperling, is that it’s cheaper, faster and less problematic to buy rather than [...]

Bolstering bandwidth and capacity with new memory tech

Rambus’ John Eble and Frank Ferro recently penned an article for Data Center Dynamics that explores how new memory technology can help bolster both bandwidth and capacity in the data center. As the two note, [...]

GLOBALFOUNDRIES highlights HBM2 PHY collaboration with Rambus

2Tbps multi-lane HBM2 PHY Earlier this month, GLOBALFOUNDRIES demonstrated silicon functionality of a 2.5D packaging solution for its high-performance 14nm FinFET FX-14 integrated design system for application-specific integrated circuits (ASICs). The 2.5D ASIC solution includes [...]

HBM2 continues to ramp

Samsung ramps volume production of 8GB HBM2 Earlier this month, Samsung confirmed an increase in production volume of its 8-gigabyte (GB) High Bandwidth Memory-2 (HBM2) to meet growing market needs across a wide range of [...]

The rise of high bandwidth memory (HBM)

Semiconductor Engineering’s Ann Steffora Mutschler recently penned an article about high bandwidth memory (HBM). As Mutschler observes, the latest iteration of HBM continues its rise as a viable contender in the memory space. Indeed, HBM [...]

Building a robust HBM2 PHY

What is HBM? HBM is a high-performance memory that features reduced power consumption and a small form factor. More specifically, it combines 2.5D packaging with a wider interface at a lower clock speed (as compared [...]

The Rambus HBM GEN2 PHY: A closer look

Earlier this week, Rambus announced the availability of its new High Bandwidth Memory (HBM) Gen2 PHY. Designed for systems that require low latency and high bandwidth memory, the Rambus HBM PHY, built on the GLOBALFOUNDRIES [...]

Saving power with HBM

Ed Sperling of Semiconductor Engineering notes that power has always been a “global concern” in the design process because it affects every part of a chip. Nevertheless, partitioning for power rather than functionality or performance has [...]

ChipEstimate and Rambus look beyond DDR4


Frank Ferro, a senior director of product management at Rambus, has penned an article for ChipEstimate about the future of DRAM in the age of the IoT. According to Ferro, the semiconductor industry has traditionally relied [...]

EE Times takes a closer look at Rambus’ 14nm R+ DDR4 PHY

Gary Hilson of the EE Times has covered Rambus’ recent announcement about the development of its R+ DDR4 PHY on GLOBALFOUNDRIES 14nm LPP process. As the journalist notes, the silicon is the first production-ready 3200 [...]

Optimizing memory bandwidth

Frank Ferro, a senior director of product management at Rambus, recently sat down with Ed Sperling of Semiconductor Engineering and other industry participants to discuss the slew of new memory initiatives and entrants. According to [...]

Exploring 2.5D packaging and beyond


Frank Ferro, a Senior Director of Product Marketing at Rambus, recently participated in a Semiconductor Engineering roundtable discussion about 2.5D and advanced packaging. According to Ferro, 2.5D can succeed if customer demand overcomes the additional [...]

Architecting new memory for the IoT

The once indefatigable Moore’s Law is beginning to slow, even as data, driven by a burgeoning Internet of Things (IoT), continues to increase exponentially. Consequently, a slew of new memory architectures, including those utilizing 2.5D [...]

PC World packs 128GB of DDR4 – into a single PC

PC World executive editor Gordon Mah Ung recently announced that his team successfully “smashed right through” the traditional 64GB system RAM barrier. “[The] barrier has vexed consumer computing for years now. Mainstream desktop PCs have [...]

Increasing crop yields with Big Data


The Farmers Business Network (FBN) is currently working on an initiative to break down agricultural data on millions of acres of U.S. farmland – while providing real-world results on the performance of various seed and [...]

The DDR5-HBM connection


Frank Ferro, senior director of product marketing at Rambus, recently told SemiconductorEngineering’s Ed Sperling that he was looking forward to seeing what the company could do for next-gen DDR5 as well as evolving high-bandwidth memory [...]

Navigating Big Data analytics


Intel VP and General Manager Ron Kasabian recently described the extraction of meaningful information from raw data as a “key enabler” of the new digital service economy. “In this new era, an organization’s competitive edge [...]

Rambus licenses patents and technology to IBM

Rambus has signed both a patent and a technology license agreement with IBM. According to Frank Ferro, senior director of product management at Rambus, the agreement authorizes the integration of Rambus’ memory and serial link [...]

AnandTech analyzes DDR4 and beyond

Writing for AnandTech, Ian Cutress recently explained why DDR4 was first launched in the enthusiast space. “On the server side, any opportunity to use lower power and drive cooling costs down is a positive, so [...]

DDR4 deployment averts “thermal nightmare”

Writing for DataCenter Dynamics, Scott Fulton notes that recent benchmark results indicate DDR4 is at least partially, and perhaps wholly, responsible for performance gains in low-end and mid-tier servers. In addition, DDR4 may, at best, [...]

The evolution of LPDDR4

Ajay Jain, a director of product marketing at Rambus, recently told Semiconductor Engineering that LPDDR3 was the “workhorse” of the mobile memory market in 2014. According to Jain, LPDDR3 will retain its heavyweight status throughout [...]

Doubling DRAM performance with conventional memory

Writing for SemiconductorEngineering, Ed Sperling reports that long-awaited DDR4 rollouts have begun. Indeed, a slew of consumer-centric motherboards packing Intel’s X99 chipset and DDR4 memory were reviewed by AnandTech’s Ian Cutress in late September. In addition, [...]