The Rambus DDR3 memory PHY is optimized for consumer applications with reduced system cost, improved performance and faster time-to-market. Fully compatible with DDR3 at 1.5V and DDR3L at 1.35V and scalable to 2133Mbps, the PHY has undergone extensive design-phase modeling and simulation of alternative SOC, package and PCB environments to ease implementation and enable first-time-right designs. In order to deliver improved flexibility of design, the R+ DDR3 PHY supports wire-bond (running up to 1600 Mbps) and flip-chip (running up to 2133 Mbps) packaging options and is compatible with 4- and 6-layer PCB designs. In addition, it features FlexPhase™ circuits that enable Per byte timing adjustment circuits deskew data and clock signals to improve signal integrity and simplify package and PCB system design.

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