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Highlights: Expands comprehensive portfolio of cutting-edge IP designed on TSMC’s industry-leading 7nm (N7) process Enables the most power- and cost-efficient solution for die-to-die (D2D) and die-to-optical engine (D2OE) connectivity over Extra Short Reach (XSR) and Ultra Short Reach (USR) channels Accelerates next-generation data center, networking, 5G, high-performance computing (HPC), and artificial intelligence/machine learning (AI/ML) applications […]
Written by Paul Karazuba for Rambus Press A team of North Carolina State University researchers recently published a paper that highlights the vulnerability of machine learning (ML) models to side-channel attacks. Specifically, the team used power-based side-channel attacks to extract the secret weights of a Binarized Neural Network (BNN) in a highly-parallelized hardware implementation. “Physical […]
Dedicated accelerator hardware for artificial intelligence and machine learning (AI/ML) algorithms are increasingly prevalent in data centers and endpoint devices. These accelerators handle valuable data and models, and face a growing threat landscape putting AI/ML assets at risk. Using fundamental cryptographic security techniques performed by a hardware root of trust can safeguard these assets from […]
In part one of this two-part series, Semiconductor Engineering Editor in Chief Ed Sperling and Rambus Sr. Director of Product Management Frank Ferro took a closer look at the various types of memory that system designers are using to support artificial intelligence (AI), machine learning (ML), and high-performance computing (HPC) applications. In this blog post, […]
Semiconductor Engineering Editor in Chief Ed Sperling recently spoke with Rambus Sr. Director of Product Management Frank Ferro about designing high-performance memory subsystems for artificial intelligence (AI), machine learning (ML), and high-performance computing (HPC) applications. As Ferro notes, there is plenty of compute (CPU) power available today to support the above-mentioned markets. “[However], the advances […]
Highlights: Integrated hardware-based solution delivers full line-rate MACsec security at 100G to 800G data rates Supports multi-channel, multi-rate implementations with flexible bandwidth allocation Delivers enhanced data security for cloud, enterprise and carrier network applications as well as network-attached, high-performance computing (HPC) and AI/ML SUNNYVALE, Calif. – Apr. 29, 2020 – Rambus Inc. (NASDAQ: RMBS), a premier silicon IP and […]
Written by Steven Woo for Rambus Press In part three of this series, we discussed how a Roofline model can help system designers better understand if the performance of applications running on specific processors is limited more by compute resources, or by memory bandwidth. Rooflines are particularly useful when analyzing machine learning applications like neural […]
What does security looklike when 5G meets AI? Incredible synergies will be realized when 5G meets AI. Security anchored in hardware can protect the great value created. Learn how Rambus solutions secure the chips powering the 5G-AI revolution. 5G and AI Raise Security Risks for IoT Devices April 30th @ 11am PT | 2pm ET […]
Looking Ahead to 2020 from Northwest Logic, now part of Rambus Northwest Logic is now part of Rambus Inc., a premier silicon IP and chip provider. We are now proud to offer comprehensive memory and SerDes IP solutions, including PHYs and controllers. We continue to offer standalone controllers, providing customers with the ability to get […]
Let’s start with PCIe5, the spec for which was finalized in early 2019. Now manufacturers are now getting revved up to produce PCIe5 hardware in 2020, which will be a boon for data- and processor-hungry workloads like machine learning and AI, as well as high performance computing (HPC) workloads that rely on GPUS, FPGAs, and […]