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Found 233 Results
Integrated Reorder Functionality
https://www.rambus.com/chip-interface-ip-glossary/integrated-reorder-functionality/Integrated Reorder Functionality refers to a hardware or firmware feature embedded within high-speed data transmission systems that dynamically reorders out-of-sequence data packets or transactions to restore their original order before processing. This functionality is critical in systems where data may arrive out of order due to parallelism, pipelining, or multi-path routing, common in protocols like PCI Express (PCIe), Compute Express Link (CXL), and Network-on-Chip (NoC) architectures.
ECC (Error Correction Code)
https://www.rambus.com/chip-interface-ip-glossary/ecc/Error Correction Code (ECC) is a method of detecting and correcting data corruption in digital systems. It ensures data integrity by adding redundant bits to data transmissions or storage, allowing the system to identify and correct errors without needing retransmission. ECC is widely used in memory modules, storage devices, communication systems, and high-reliability computing environments.
Crosslink
https://www.rambus.com/chip-interface-ip-glossary/crosslink/In the context of programmable logic and FPGA (Field Programmable Gate Array) architectures, Crosslink refers to a class of low-power, high-performance FPGAs designed to enable efficient bridging and interfacing between multiple high-speed data protocols, especially in embedded vision and edge AI applications.
Hardware Root of Trust: Everything you need to know
https://www.rambus.com/blogs/hardware-root-of-trust/[Last updated on April 8, 2025] A root of trust is the security foundation for an SoC, other semiconductor device or electronic system. However, its meaning differs depending on who you ask. From our perspective, the hardware root of trust contains the keys for cryptographic functions and is usually a part of the secure boot […]
Rambus CXL IP: A Journey from Spec to Compliance
https://www.rambus.com/blogs/rambus-cxl-ip-a-journey-from-spec-to-compliance/[Updated April 7, 2025] With the ongoing efforts of the Rambus engineering team, we have now achieved compliance to CXL 2.0 with our CXL Controller IP, and it has been added to the Integrators List. Company Name Product Name Device ID Device Type Feature Set Spec Revision PHY Speed Max Lane Form Factor Function Compliance […]
CryptoManager Hub (CH-7xx) and CryptoManager Core (CC-7xx) ISO 21434 Automotive-grade
https://www.rambus.com/security/crypto-hub/ch-7xx/CryptoManager Hub (CH-7xx) ISO 21434 Automotive-grade Foundational Crypto Accelerator Cores for Automotive Use Cases Contact Us The automotive-grade CryptoManager Hub (CMH) from Rambus is the next-generation of flexible and configurable cryptographic family of accelerator cores intended for embedding in customer or Rambus provided HSM security modules. These cores target automotive power and space-constrained SoCs or […]
CryptoManager Hub (CH-6xx) and CryptoManager Core (CC-6xx)
https://www.rambus.com/security/crypto-hub/ch-6xx/CryptoManager Hub (CH-6xx) Flexible and configurable solutions for protecting data at rest Contact Us CryptoManager Hub (CMH) from Rambus is the next-generation family of flexible and configurable cryptographic accelerator cores intended for embedding in customer or Rambus provided Root of Trust security modules. These cores target power and space-constrained SoCs or FPGAs. The CMH supports SESIP-PSA […]
Rambus, VIAVI and Samtec Demonstrate CXL® over Optics PoC at Upcoming SC24
https://www.rambus.com/blogs/rambus-viavi-and-samtec-demonstrate-cxl-over-optics-poc-at-upcoming-sc24/The disruption of GenAI over the last few years has forced system architects and hardware designers to rethink data center topologies. While AI model sizes and compute capability are growing exponentially, I/O throughput and memory access are growing linearly. These trends create an unsustainable gap, and it needs to be addressed across the stack starting […]
Security IP Glossary
https://www.rambus.com/security/glossary/Security IP Glossary A glossary of Security IP terminology and relevant solutions. a | b | c | d | e | f | g | h | i | j | k | l | m | n | o | p | q | r | s | t | u | v | […]
PCIe 6.2 Switch
https://www.rambus.com/interface-ip/pci-express/pcie6-2-switch/PCIe 6.3 Switch Contact Us The Rambus PCI Express® (PCIe®) 6.3 Switch is a customizable, multiport embedded switch for PCIe designed for ASIC implementations. It enables the connection of one upstream port and multiple downstream ports as a fully configurable interface subsystem. It is backward compatible to PCIe 5.0. ContactProduct Brief How the PCIe 6.3 […]
