At Rambus, we create cutting-edge semiconductor and IP products, spanning memory and interfaces to security, smart sensors and lighting.
Found 79 Results
CCIX 1.1 Controller
https://www.rambus.com/interface-ip/cxl/ccix1-controller/CCIX 1.1 Controller Contact Us The CCIX 1.1 Controller (formerly XpressCCIX) is a configurable and scalable PCIe controller IP designed for ASIC and FPGA implementations. There is also a CCIX 1.1 Controller with AXI version (formerly XpressCCIX-AXI) with support for the AMBA AXI protocol specification. ContactProduct Briefs CCIX 1.1 CCIX 1.1 with AXI How the […]
PCIe 6.0 Controller
https://www.rambus.com/interface-ip/pci-express/pcie6-controller/PCIe 6.1 Controller Contact Us The PCI Express® (PCIe®) 6.1 Controller is configurable and scalable controller IP designed for ASIC implementation. The controller supports the PCIe 6.1 specification, including 64 GT/s data rates, PAM4 signaling, FLIT mode, and L0p power state. The PCIe 6.1 architecture will be essential for SoC designers creating next-generation chips that […]
PCIe 5.0 Multi-port Switch
https://www.rambus.com/interface-ip/pci-express/pcie5-multi-port-switch/PCIe 5.0 Multi-port Switch Contact Us The PCIe 5.0 Multi-port Switch (formerly XpressSWITCH) is a customizable, multiport embedded Switch for PCIe designed for ASIC and FPGA implementations enabling the connection of one upstream port and up to 31 downstream ports. ContactProduct Brief How the PCIe 5.0 Multi-Port Switch Works The PCIe 5.0 Switch IP transparently […]
PCIe Switch for USB4
https://www.rambus.com/interface-ip/pci-express/pcie-switch-for-usb4/PCIe Switch for USB4 Contact Us The PCIe Switch for USB4 (formerly XpressSWITCH) is a customizable, embedded switch for PCI Express (PCIe) designed for implementations in USB4 devices. ContactProduct Brief How the PCIe Switch for USB4 Works A fully configurable fanout switch, the PCIe Switch for USB4 provides one upstream port and up to 31 […]
PCIe 3.1 Controller
https://www.rambus.com/interface-ip/pci-express/pcie3-controller/PCIe 3.1 Controller Contact Us The PCIe 3.1 Controller (formerly XpressRICH) is designed to achieve maximum PCI Express (PCIe) 3.1 performance with great design flexibility and ease of integration. It is fully compatible with the PCIe 3.1/3.0 specification. A PCIe 3.1 Controller with AXI (formerly XpressRICH-AXI) is also available. The controller delivers high-bandwidth and low-latency connectivity […]
Debug and Test Solutions
https://www.rambus.com/interface-ip/pci-express/debug-and-test-solutions/Debug and Test Solutions Contact Us INSPECTOR for PCIe 5.0 Interposer Card for Diagnostic Testing, Exercising and Debug of PCIe Devices at up to Gen5 32 GT/s speed. ContactProduct Brief Inspector for PCIe 5.0 INSPECTOR is a PCIe 5.0-compliant interposer module designed for non-intrusive monitoring, diagnostic, exercising and debug of PCIe devices. INSPECTOR uses transparent switching […]
Rambus Design Summit Featured Speaker: Frank Ferro
https://www.rambus.com/blogs/rambus-design-summit-featured-speaker-frank-ferro/Thanks to everyone who joined us for Rambus Design Summit 2021. Over the coming weeks we’ll highlight the webinars and panels from the event all available now on-demand. About Frank Ferro Frank Ferro is the senior director of product management at Rambus Inc. responsible for memory interface IP products. Having spent more than 20 years […]
Data Center Evolution: Accelerating Computing with PCI Express 5.0
https://go.rambus.com/accelerating-computing-with-pcie5#new_tabThe PCI Express® (PCIe) interface is the critical backbone that moves data at high bandwidth between various compute nodes such as CPUs, GPUs, FPGAs, and workload-specific accelerators. The rise of cloud-based computing and hyperscale data centers, along with high-bandwidth applications like artificial intelligence (AI) and machine learning (ML), require the new level of performance of […]
How PCIe 5 Can Accelerate AI and ML Applications
https://www.rambus.com/blogs/how-pcie-5-can-accelerate-ai-and-ml-applications/Rambus’ Suresh Andani has written a detailed Semiconductor Engineering article that explores how PCIe 5 can effectively accelerate AI and ML applications. According to Andani, the rapid adoption of sophisticated artificial intelligence/machine learning (AI/ML) applications and the shift to cloud-based workloads has significantly increased network traffic in recent years. However, the paradigm of virtualization can […]
The Ultimate Guide to HBM2E Implementation & Selection
https://www.rambus.com/blogs/hbm2e/This is the most comprehensive guide to selecting and implementing a HBM2E memory IP interface solution. Frank Ferro and Joseph Rodriguez, Senior Directors Product Management at Rambus, hosted a webinar at our Rambus Design Summit discussing HBM2 and HBM2E memory technology. There’s a lot of decisions that need to be made when you’re developing high […]
