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AI Requires Tailored DRAM Solutions: Part 4
https://www.rambus.com/blogs/ai-requires-tailored-dram-solutions-part-4/Frank Ferro, Senior Director Product Management at Rambus, and Shane Rau, Senior Research Executive at IDC, recently hosted a webinar that explores the role of tailored DRAM solutions in advancing artificial intelligence. Part three of this four-part series touched on a wide range of topics including the impact of AI on specific hardware systems, training […]
AI Requires Tailored DRAM Solutions: Part 3
https://www.rambus.com/blogs/ai-requires-tailored-dram-solutions-part-3/Frank Ferro, Senior Director Product Management at Rambus, and Shane Rau, Senior Research Executive at IDC, recently hosted a webinar that explores the role of tailored DRAM solutions in advancing artificial intelligence. Part two of this four-part series touched on multiple topics including how AI enables useful data processing, various types of AI silicon, and […]
AI Requires Tailored DRAM Solutions: Part 2
https://www.rambus.com/blogs/ai-requires-tailored-dram-solutions-part-2/Written by Rambus Press Frank Ferro, Senior Director Product Management at Rambus, and Shane Rau, Senior Research Executive at IDC, recently hosted a webinar that explores the role of tailored DRAM solutions in advancing artificial intelligence. Part one of this four-part series reviewed a range of topics including the interconnected system landscape, the impact of […]
Rambus Design Summit
https://www.rambus.com/rambus-design-summit-2/October 8, 2020 Register Today Join us for a day of virtual sessions covering the selection and implementation of IP solutions for the data center, 5G/edge and IoT devices including advancing the performance of AI/ML applications. Connect with a community of industry experts and gain insights and practical information for the implementation of their next-generation […]
PCIe 5 Drill-Down with Rambus’ Suresh Andani: Part 3
https://www.rambus.com/blogs/pcie-5-drill-down-with-rambus-suresh-andani-part-3/In part two of this three-part series, Semiconductor Engineering Editor in Chief Ed Sperling and Suresh Andani, Senior Director, Product Marketing and Business Development at Rambus, discussed early market adoption of PCIe 5, as well as the networking environment the specification will support in the data center. In this blog post, Sperling and Andani explore […]
PCIe 5 Drill-Down with Rambus’ Suresh Andani: Part 1
https://www.rambus.com/blogs/pcie-5-drill-down-with-rambus-suresh-andani-part-1/Semiconductor Engineering Editor in Chief Ed Sperling recently sat down with Suresh Andani, Senior Director, Product Marketing and Business Development at Rambus, to discuss the evolution of PCIe and its latest iteration: PCIe 5. As Andani notes, PCIe 5 and subsequent iterations of the PCIe standard will continue to be one of the “key interfaces” […]
The Thermal Challenges of Moore’s Law: Part 1
https://www.rambus.com/blogs/the-thermal-challenges-of-moores-law-part-1/Semiconductor Engineering editor in chief Ed Sperling spoke with Steven Woo, Rambus fellow and distinguished inventor, about the relationship between Moore’s Law, Dennard scaling and thermal challenges. As Woo notes, there is a “tug of war” between the benefits that Moore’s Law provides and the breakdown of Dennard scaling in 2005. “Systems now need to […]
Storage and Networking Bytes: PCIe5, OpenShift, and Veeam
https://www.datanami.com/2020/01/17/storage-and-networking-bytes-pcie5-openshift-and-veeam/#new_tabLet’s start with PCIe5, the spec for which was finalized in early 2019. Now manufacturers are now getting revved up to produce PCIe5 hardware in 2020, which will be a boon for data- and processor-hungry workloads like machine learning and AI, as well as high performance computing (HPC) workloads that rely on GPUS, FPGAs, and […]
PCIe 4.0 Controller
https://www.rambus.com/interface-ip/pci-express/pcie4-controller/PCIe 4.0 Controller Contact Us The PCIe 4.0 Controller (formerly XpressRICH) is designed to achieve maximum PCI Express® (PCIe®) 4.0 performance with great design flexibility and ease of integration. It is fully backward compatible with PCIe 3.1/3.0. A PCIe 4.0 Controller with AXI (formerly XpressRICH-AXI) is also available. The controller delivers high-bandwidth and low-latency connectivity for […]
DDR4 Controller
https://www.rambus.com/interface-ip/ddr/ddr4-controller/DDR4 Controller Contact Us The Rambus DDR4 controller core is designed for high memory throughput, high clock rates, and full programmability in computing and networking applications. Secure Site Login ContactProduct Brief How a DDR4 Interface Subsystem works The Rambus DDR4 controller maximizes memory bus efficiency via Look-Ahead command processing, bank management, auto-precharge and additive latency […]
